[Click] How to port Click to the Kamikaze openwrt OS ?
Yongheng Qi
jetever at gmail.com
Thu Oct 15 11:17:32 EDT 2009
I need the openwrt atheros AR71xx platform click kernelmode patch and src.
I try to use the 2.6.24patch to 2.6.26. and test.
but the clickfs not work. the /click can't access.
Anyone could help me?
Thanks
2009/10/15 Giovanni Di Stasi <giovanni.distasi at unina.it>
> Hi Dennis,
>
> I'm using Click Modular Router with an old OpenWrt in kernel mode.
> The revision I'm using is an old one, the 11777 (from trunk. To that
> revision I apply the patch of click (that you can find attached),
> putting it in target/linux/ixp4xx/patches-2.6.24.
>
> I also have to change the kernel version to be compiled (please, see the
> second patch).
>
> Even if you start with this old version, it is still possible to use
> recent packages (by upgrading them separately).
>
> Giovanni
>
>
> Dennis D.J. wrote:
> > hi, I'm tyring to do the same thing about complie click as a module of
> kamikaze(OpenWrt OS), I wonder what's the step of cross complie. I have
> managed to crosscomplie the kamikaze 8.09 in my x86 PC, but I got no idea
> how to compile a module for a embeded linux. Is there anybody who can tell
> m? Thx a lot!
> >
> > 2009-10-14
> >
> >
> >
> > Dennis D.J.
> >
> > _______________________________________________
> > click mailing list
> > click at amsterdam.lcs.mit.edu
> > https://amsterdam.lcs.mit.edu/mailman/listinfo/click
> >
> >
>
>
> --
> Giovanni Di Stasi, PhD Student
> Dipartimento di Informatica e Sistemistica
> Università degli Studi di Napoli "Federico II"
> Via Claudio 21 -- 80125 Napoli (Italy)
> Phone: +39 081 76 83821 - Fax: +39 081 76 83816
> Email: giovanni.distasi at unina.it
> gdistasi at gmail.com
>
>
> diff -U 5 -r linux-2.6.24.7/arch/arm/mach-iop13xx/irq.c
> linux-2.6.24.7-patched/arch/arm/mach-iop13xx/irq.c
> --- linux-2.6.24.7/arch/arm/mach-iop13xx/irq.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/arm/mach-iop13xx/irq.c 2008-11-19
> 16:47:17.000000000 -0600
> @@ -36,11 +36,11 @@
> asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
> return val;
> }
> static void write_intctl_0(u32 val)
> {
> - asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
> + asm volatile("mcr p6, 0, %0, c0, c4, 0": :"r" (val));
> }
>
> /* INTCTL1 CP6 R1 Page 4
> */
> static u32 read_intctl_1(void)
> @@ -49,11 +49,11 @@
> asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
> return val;
> }
> static void write_intctl_1(u32 val)
> {
> - asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
> + asm volatile("mcr p6, 0, %0, c1, c4, 0": :"r" (val));
> }
>
> /* INTCTL2 CP6 R2 Page 4
> */
> static u32 read_intctl_2(void)
> @@ -62,11 +62,11 @@
> asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
> return val;
> }
> static void write_intctl_2(u32 val)
> {
> - asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
> + asm volatile("mcr p6, 0, %0, c2, c4, 0": :"r" (val));
> }
>
> /* INTCTL3 CP6 R3 Page 4
> */
> static u32 read_intctl_3(void)
> @@ -75,53 +75,53 @@
> asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
> return val;
> }
> static void write_intctl_3(u32 val)
> {
> - asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
> + asm volatile("mcr p6, 0, %0, c3, c4, 0": :"r" (val));
> }
>
> /* INTSTR0 CP6 R0 Page 5
> */
> static void write_intstr_0(u32 val)
> {
> - asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
> + asm volatile("mcr p6, 0, %0, c0, c5, 0": :"r" (val));
> }
>
> /* INTSTR1 CP6 R1 Page 5
> */
> static void write_intstr_1(u32 val)
> {
> - asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
> + asm volatile("mcr p6, 0, %0, c1, c5, 0": :"r" (val));
> }
>
> /* INTSTR2 CP6 R2 Page 5
> */
> static void write_intstr_2(u32 val)
> {
> - asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
> + asm volatile("mcr p6, 0, %0, c2, c5, 0": :"r" (val));
> }
>
> /* INTSTR3 CP6 R3 Page 5
> */
> static void write_intstr_3(u32 val)
> {
> - asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
> + asm volatile("mcr p6, 0, %0, c3, c5, 0": :"r" (val));
> }
>
> /* INTBASE CP6 R0 Page 2
> */
> static void write_intbase(u32 val)
> {
> - asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
> + asm volatile("mcr p6, 0, %0, c0, c2, 0": :"r" (val));
> }
>
> /* INTSIZE CP6 R2 Page 2
> */
> static void write_intsize(u32 val)
> {
> - asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
> + asm volatile("mcr p6, 0, %0, c2, c2, 0": :"r" (val));
> }
>
> /* 0 = Interrupt Masked and 1 = Interrupt not masked */
> static void
> iop13xx_irq_mask0 (unsigned int irq)
> diff -U 5 -r linux-2.6.24.7/arch/arm/mach-iop13xx/msi.c
> linux-2.6.24.7-patched/arch/arm/mach-iop13xx/msi.c
> --- linux-2.6.24.7/arch/arm/mach-iop13xx/msi.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/arm/mach-iop13xx/msi.c 2008-11-19
> 16:47:17.000000000 -0600
> @@ -36,11 +36,11 @@
> asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val));
> return val;
> }
> static void write_imipr_0(u32 val)
> {
> - asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val));
> + asm volatile("mcr p6, 0, %0, c8, c1, 0": :"r" (val));
> }
>
> /* IMIPR1 CP6 R9 Page 1
> */
> static u32 read_imipr_1(void)
> @@ -49,11 +49,11 @@
> asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val));
> return val;
> }
> static void write_imipr_1(u32 val)
> {
> - asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val));
> + asm volatile("mcr p6, 0, %0, c9, c1, 0": :"r" (val));
> }
>
> /* IMIPR2 CP6 R10 Page 1
> */
> static u32 read_imipr_2(void)
> @@ -62,11 +62,11 @@
> asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val));
> return val;
> }
> static void write_imipr_2(u32 val)
> {
> - asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val));
> + asm volatile("mcr p6, 0, %0, c10, c1, 0": :"r" (val));
> }
>
> /* IMIPR3 CP6 R11 Page 1
> */
> static u32 read_imipr_3(void)
> @@ -75,11 +75,11 @@
> asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val));
> return val;
> }
> static void write_imipr_3(u32 val)
> {
> - asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val));
> + asm volatile("mcr p6, 0, %0, c11, c1, 0": :"r" (val));
> }
>
> static u32 (*read_imipr[])(void) = {
> read_imipr_0,
> read_imipr_1,
> diff -U 5 -r linux-2.6.24.7/arch/arm/mach-s3c2412/pm.c
> linux-2.6.24.7-patched/arch/arm/mach-s3c2412/pm.c
> --- linux-2.6.24.7/arch/arm/mach-s3c2412/pm.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/arm/mach-s3c2412/pm.c 2008-11-19
> 16:47:17.000000000 -0600
> @@ -50,11 +50,11 @@
>
> asm("b 1f\n\t"
> ".align 5\n\t"
> "1:\n\t"
> "mcr p15, 0, %0, c7, c10, 4\n\t"
> - "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
> + "mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp));
>
> /* we should never get past here */
>
> panic("sleep resumed to originator?");
> }
> diff -U 5 -r linux-2.6.24.7/arch/avr32/kernel/kprobes.c
> linux-2.6.24.7-patched/arch/avr32/kernel/kprobes.c
> --- linux-2.6.24.7/arch/avr32/kernel/kprobes.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/avr32/kernel/kprobes.c 2008-11-19
> 16:47:17.000000000 -0600
> @@ -242,11 +242,11 @@
> return 1;
> }
>
> void __kprobes jprobe_return(void)
> {
> - asm volatile("breakpoint" ::: "memory");
> + asm volatile("breakpoint" : : : "memory");
> }
>
> int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs
> *regs)
> {
> /*
> diff -U 5 -r linux-2.6.24.7/arch/frv/kernel/gdb-stub.c
> linux-2.6.24.7-patched/arch/frv/kernel/gdb-stub.c
> --- linux-2.6.24.7/arch/frv/kernel/gdb-stub.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/frv/kernel/gdb-stub.c 2008-11-19
> 16:47:17.000000000 -0600
> @@ -1329,30 +1329,30 @@
> asm volatile("movsg cxnr,%0" : "=r"(__debug_mmu.regs.cxnr));
>
> p = __debug_mmu.tlb;
>
> /* way 0 */
> - asm volatile("movgs %0,tpxr" :: "r"(0 << TPXR_WAY_SHIFT));
> + asm volatile("movgs %0,tpxr" : : "r"(0 << TPXR_WAY_SHIFT));
> for (loop = 0; loop < 64; loop++) {
> - asm volatile("tlbpr %0,gr0,#1,#0" :: "r"(loop <<
> PAGE_SHIFT));
> + asm volatile("tlbpr %0,gr0,#1,#0" : : "r"(loop <<
> PAGE_SHIFT));
> asm volatile("movsg tplr,%0" : "=r"(p->L));
> asm volatile("movsg tppr,%0" : "=r"(p->P));
> p++;
> }
>
> /* way 1 */
> - asm volatile("movgs %0,tpxr" :: "r"(1 << TPXR_WAY_SHIFT));
> + asm volatile("movgs %0,tpxr" : : "r"(1 << TPXR_WAY_SHIFT));
> for (loop = 0; loop < 64; loop++) {
> - asm volatile("tlbpr %0,gr0,#1,#0" :: "r"(loop <<
> PAGE_SHIFT));
> + asm volatile("tlbpr %0,gr0,#1,#0" : : "r"(loop <<
> PAGE_SHIFT));
> asm volatile("movsg tplr,%0" : "=r"(p->L));
> asm volatile("movsg tppr,%0" : "=r"(p->P));
> p++;
> }
>
> - asm volatile("movgs %0,tplr" ::
> "r"(__debug_mmu.regs.tplr));
> - asm volatile("movgs %0,tppr" ::
> "r"(__debug_mmu.regs.tppr));
> - asm volatile("movgs %0,tpxr" ::
> "r"(__debug_mmu.regs.tpxr));
> + asm volatile("movgs %0,tplr" : :
> "r"(__debug_mmu.regs.tplr));
> + asm volatile("movgs %0,tppr" : :
> "r"(__debug_mmu.regs.tppr));
> + asm volatile("movgs %0,tpxr" : :
> "r"(__debug_mmu.regs.tpxr));
> } while(0);
> #endif
>
> } /* end gdbstub_get_mmu_state() */
>
> @@ -1419,11 +1419,11 @@
>
> /* handle the decrement timer going off (FR451 only) */
> if (temp3 == temp + TBR_TT_DECREMENT_TIMER ||
> temp3 == temp2 + TBR_TT_DECREMENT_TIMER
> ) {
> - asm volatile("movgs %0,timerd" :: "r"(10000000));
> + asm volatile("movgs %0,timerd" : : "r"(10000000));
> asm volatile("movsg pcsr,%0" : "=r"(__debug_frame->pc));
> __debug_frame->psr |= PSR_ET;
> __debug_frame->psr &= ~PSR_S;
> if (__debug_frame->psr & PSR_PS)
> __debug_frame->psr |= PSR_S;
> @@ -1694,17 +1694,17 @@
>
> for (loop = 132; loop <= 140; loop++)
> ptr = hex2mem(ptr, &temp, 4);
>
> ptr = hex2mem(ptr, &temp, 4);
> - asm volatile("movgs %0,scr0" :: "r"(temp));
> + asm volatile("movgs %0,scr0" : : "r"(temp));
> ptr = hex2mem(ptr, &temp, 4);
> - asm volatile("movgs %0,scr1" :: "r"(temp));
> + asm volatile("movgs %0,scr1" : : "r"(temp));
> ptr = hex2mem(ptr, &temp, 4);
> - asm volatile("movgs %0,scr2" :: "r"(temp));
> + asm volatile("movgs %0,scr2" : : "r"(temp));
> ptr = hex2mem(ptr, &temp, 4);
> - asm volatile("movgs %0,scr3" :: "r"(temp));
> + asm volatile("movgs %0,scr3" : : "r"(temp));
>
> ptr = hex2mem(ptr, &__debug_frame->lr, 4);
> ptr = hex2mem(ptr, &__debug_frame->lcr, 4);
>
> ptr = hex2mem(ptr, &__debug_frame->iacc0, 8);
> diff -U 5 -r linux-2.6.24.7/arch/frv/kernel/setup.c
> linux-2.6.24.7-patched/arch/frv/kernel/setup.c
> --- linux-2.6.24.7/arch/frv/kernel/setup.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/frv/kernel/setup.c 2008-11-19
> 16:47:17.000000000 -0600
> @@ -841,11 +841,11 @@
> #ifdef DEBUG
> printk("Done setup_arch\n");
> #endif
>
> /* start the decrement timer running */
> -// asm volatile("movgs %0,timerd" :: "r"(10000000));
> +// asm volatile("movgs %0,timerd" : : "r"(10000000));
> // __set_HSR(0, __get_HSR(0) | HSR0_ETMD);
>
> } /* end setup_arch() */
>
> #if 0
> diff -U 5 -r linux-2.6.24.7/arch/frv/mm/fault.c
> linux-2.6.24.7-patched/arch/frv/mm/fault.c
> --- linux-2.6.24.7/arch/frv/mm/fault.c 2008-05-06 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/frv/mm/fault.c 2008-11-19
> 16:47:17.000000000 -0600
> @@ -241,11 +241,11 @@
> );
>
> pte = (pte_t *) damlr + __pte_index(ear0);
> val = pte_val(*pte);
>
> - asm volatile("movgs %0,dampr2" :: "r" (dampr));
> + asm volatile("movgs %0,dampr2" : : "r" (dampr));
>
> printk(KERN_ALERT " PTE : %8p { %08lx }\n", pte, val);
> }
>
> die_if_kernel("Oops\n");
> diff -U 5 -r linux-2.6.24.7/arch/frv/mm/mmu-context.c
> linux-2.6.24.7-patched/arch/frv/mm/mmu-context.c
> --- linux-2.6.24.7/arch/frv/mm/mmu-context.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/frv/mm/mmu-context.c 2008-11-19
> 16:47:17.000000000 -0600
> @@ -116,11 +116,11 @@
> asm volatile("movgs %0,dampr5" : : "r"(ctx->dtlb_ptd_mapping));
>
> /* map the PGD into uncached virtual memory */
> asm volatile("movgs %0,ttbr" : : "r"(_pgd));
> asm volatile("movgs %0,dampr3"
> - :: "r"(_pgd | xAMPRx_L | xAMPRx_M | xAMPRx_SS_16Kb |
> + : : "r"(_pgd | xAMPRx_L | xAMPRx_M | xAMPRx_SS_16Kb |
> xAMPRx_S | xAMPRx_C | xAMPRx_V));
>
> } /* end change_mm_context() */
>
>
> /*****************************************************************************/
> diff -U 5 -r linux-2.6.24.7/arch/h8300/kernel/setup.c
> linux-2.6.24.7-patched/arch/h8300/kernel/setup.c
> --- linux-2.6.24.7/arch/h8300/kernel/setup.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/h8300/kernel/setup.c 2008-11-19
> 16:47:17.000000000 -0600
> @@ -63,11 +63,11 @@
> /* printk with gdb service */
> static void gdb_console_output(struct console *c, const char *msg,
> unsigned len)
> {
> for (; len > 0; len--) {
> asm("mov.w %0,r2\n\t"
> - "jsr @0xc4"::"r"(*msg++):"er2");
> + "jsr @0xc4": :"r"(*msg++):"er2");
> }
> }
>
> /*
> * Setup initial baud/bits/parity. We do two things here:
> diff -U 5 -r linux-2.6.24.7/arch/h8300/platform/h8300h/ptrace_h8300h.c
> linux-2.6.24.7-patched/arch/h8300/platform/h8300h/ptrace_h8300h.c
> --- linux-2.6.24.7/arch/h8300/platform/h8300h/ptrace_h8300h.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/h8300/platform/h8300h/ptrace_h8300h.c
> 2008-11-19 16:47:17.000000000 -0600
> @@ -189,11 +189,11 @@
> "bor #2,%w0\n\t"
> "bst #5,%w0\n\t"
> "bld #2,%w0\n\t"
> "bor #0,%w0\n\t"
> "bst #6,%w0\n\t"
> - :"=&r"(cond)::"cc");
> + :"=&r"(cond): :"cc");
> cond &= condmask[reson >> 1];
> if (!(reson & 1))
> return cond == 0;
> else
> return cond != 0;
> diff -U 5 -r linux-2.6.24.7/arch/m68k/kernel/process.c
> linux-2.6.24.7-patched/arch/m68k/kernel/process.c
> --- linux-2.6.24.7/arch/m68k/kernel/process.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/m68k/kernel/process.c 2008-11-19
> 16:47:17.000000000 -0600
> @@ -299,19 +299,19 @@
> ((fpu->fpregs[i] & 0x0000ffff) <<
> 16);
> return 1;
> }
>
> /* First dump the fpu context to avoid protocol violation. */
> - asm volatile ("fsave %0" :: "m" (fpustate[0]) : "memory");
> + asm volatile ("fsave %0" : : "m" (fpustate[0]) : "memory");
> if (!CPU_IS_060 ? !fpustate[0] : !fpustate[2])
> return 0;
>
> asm volatile ("fmovem %/fpiar/%/fpcr/%/fpsr,%0"
> - :: "m" (fpu->fpcntl[0])
> + : : "m" (fpu->fpcntl[0])
> : "memory");
> asm volatile ("fmovemx %/fp0-%/fp7,%0"
> - :: "m" (fpu->fpregs[0])
> + : : "m" (fpu->fpregs[0])
> : "memory");
> return 1;
> }
> EXPORT_SYMBOL(dump_fpu);
>
> diff -U 5 -r linux-2.6.24.7/arch/m68knommu/kernel/process.c
> linux-2.6.24.7-patched/arch/m68knommu/kernel/process.c
> --- linux-2.6.24.7/arch/m68knommu/kernel/process.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/m68knommu/kernel/process.c 2008-11-19
> 16:47:17.000000000 -0600
> @@ -266,19 +266,19 @@
> ((fpu->fpregs[i] & 0x0000ffff) <<
> 16);
> return 1;
> }
>
> /* First dump the fpu context to avoid protocol violation. */
> - asm volatile ("fsave %0" :: "m" (fpustate[0]) : "memory");
> + asm volatile ("fsave %0" : : "m" (fpustate[0]) : "memory");
> if (!fpustate[0])
> return 0;
>
> asm volatile ("fmovem %/fpiar/%/fpcr/%/fpsr,%0"
> - :: "m" (fpu->fpcntl[0])
> + : : "m" (fpu->fpcntl[0])
> : "memory");
> asm volatile ("fmovemx %/fp0-%/fp7,%0"
> - :: "m" (fpu->fpregs[0])
> + : : "m" (fpu->fpregs[0])
> : "memory");
> #endif
> return 1;
> }
>
> diff -U 5 -r linux-2.6.24.7/arch/mips/au1000/common/reset.c
> linux-2.6.24.7-patched/arch/mips/au1000/common/reset.c
> --- linux-2.6.24.7/arch/mips/au1000/common/reset.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/mips/au1000/common/reset.c 2008-11-19
> 16:47:17.000000000 -0600
> @@ -156,11 +156,11 @@
>
> /* Give board a chance to do a hardware reset */
> board_reset();
>
> /* Jump to the beggining in case board_reset() is empty */
> - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
> + __asm__ __volatile__("jr\t%0": :"r"(0xbfc00000));
> }
>
> void au1000_halt(void)
> {
> #if defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550)
> diff -U 5 -r linux-2.6.24.7/arch/mips/gt64120/wrppmc/reset.c
> linux-2.6.24.7-patched/arch/mips/gt64120/wrppmc/reset.c
> --- linux-2.6.24.7/arch/mips/gt64120/wrppmc/reset.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/mips/gt64120/wrppmc/reset.c 2008-11-19
> 16:47:17.000000000 -0600
> @@ -21,11 +21,11 @@
> local_irq_disable();
> set_c0_status(ST0_BEV | ST0_ERL);
> change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
> flush_cache_all();
> write_c0_wired(0);
> - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
> + __asm__ __volatile__("jr\t%0": :"r"(0xbfc00000));
> }
>
> void wrppmc_machine_halt(void)
> {
> local_irq_disable();
> diff -U 5 -r linux-2.6.24.7/arch/mips/lemote/lm2e/reset.c
> linux-2.6.24.7-patched/arch/mips/lemote/lm2e/reset.c
> --- linux-2.6.24.7/arch/mips/lemote/lm2e/reset.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/mips/lemote/lm2e/reset.c 2008-11-19
> 16:47:17.000000000 -0600
> @@ -18,11 +18,11 @@
> *(unsigned long *)0xbfe00104 |= (1 << 2);
> #else
> *(unsigned long *)0xffffffffbfe00104 &= ~(1 << 2);
> *(unsigned long *)0xffffffffbfe00104 |= (1 << 2);
> #endif
> - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
> + __asm__ __volatile__("jr\t%0": :"r"(0xbfc00000));
> }
>
> static void loongson2e_halt(void)
> {
> while (1) ;
> diff -U 5 -r linux-2.6.24.7/arch/mips/pmc-sierra/msp71xx/msp_setup.c
> linux-2.6.24.7-patched/arch/mips/pmc-sierra/msp71xx/msp_setup.c
> --- linux-2.6.24.7/arch/mips/pmc-sierra/msp71xx/msp_setup.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/mips/pmc-sierra/msp71xx/msp_setup.c
> 2008-11-19 16:47:17.000000000 -0600
> @@ -121,11 +121,11 @@
> set_c0_status(ST0_BEV | ST0_ERL);
> change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
> flush_cache_all();
> write_c0_wired(0);
>
> - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
> + __asm__ __volatile__("jr\t%0": :"r"(0xbfc00000));
> #endif
> }
>
> void msp_halt(void)
> {
> diff -U 5 -r linux-2.6.24.7/arch/powerpc/kernel/btext.c
> linux-2.6.24.7-patched/arch/powerpc/kernel/btext.c
> --- linux-2.6.24.7/arch/powerpc/kernel/btext.c 2008-11-18
> 17:36:05.000000000 -0600
> +++ linux-2.6.24.7-patched/arch/powerpc/kernel/btext.c 2008-11-19
> 16:47:17.000000000 -0600
> @@ -316,16 +316,16 @@
>
> for (i=0; i < (dispDeviceRect[3] - dispDeviceRect[1]); i++)
> {
> unsigned int *ptr = base;
> for(j = width; j > 0; j -= 8) {
> - __asm__ __volatile__ ("dcbst 0,%0" :: "r" (ptr));
> + __asm__ __volatile__ ("dcbst 0,%0" : : "r" (ptr));
> ptr += 8;
> }
> base += (dispDeviceRowBytes >> 2);
> }
> - __asm__ __volatile__ ("sync" ::: "memory");
> + __asm__ __volatile__ ("sync" : : : "memory");
> }
>
> void btext_flushline(void)
> {
> unsigned int *base = (unsigned int *)calc_base(0, g_loc_Y <<
> 4);
> @@ -335,16 +335,16 @@
>
> for (i=0; i < 16; i++)
> {
> unsigned int *ptr = base;
> for(j = width; j > 0; j -= 8) {
> - __asm__ __volatile__ ("dcbst 0,%0" :: "r" (ptr));
> + __asm__ __volatile__ ("dcbst 0,%0" : : "r" (ptr));
> ptr += 8;
> }
> base += (dispDeviceRowBytes >> 2);
> }
> - __asm__ __volatile__ ("sync" ::: "memory");
> + __asm__ __volatile__ ("sync" : : : "memory");
> }
>
>
> #ifndef NO_SCROLL
> static void scrollscreen(void)
> diff -U 5 -r linux-2.6.24.7/arch/powerpc/kernel/kprobes.c
> linux-2.6.24.7-patched/arch/powerpc/kernel/kprobes.c
> --- linux-2.6.24.7/arch/powerpc/kernel/kprobes.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/powerpc/kernel/kprobes.c 2008-11-19
> 16:47:17.000000000 -0600
> @@ -517,11 +517,11 @@
> return 1;
> }
>
> void __kprobes jprobe_return(void)
> {
> - asm volatile("trap" ::: "memory");
> + asm volatile("trap" : : : "memory");
> }
>
> void __kprobes jprobe_return_end(void)
> {
> };
> diff -U 5 -r linux-2.6.24.7/arch/powerpc/mm/hash_native_64.c
> linux-2.6.24.7-patched/arch/powerpc/mm/hash_native_64.c
> --- linux-2.6.24.7/arch/powerpc/mm/hash_native_64.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/powerpc/mm/hash_native_64.c 2008-11-19
> 16:47:17.000000000 -0600
> @@ -122,11 +122,11 @@
>
> static inline void native_unlock_hpte(struct hash_pte *hptep)
> {
> unsigned long *word = &hptep->v;
>
> - asm volatile("lwsync":::"memory");
> + asm volatile("lwsync": : :"memory");
> clear_bit(HPTE_LOCK_BIT, word);
> }
>
> static long native_hpte_insert(unsigned long hpte_group, unsigned long va,
> unsigned long pa, unsigned long rflags,
> @@ -446,11 +446,11 @@
> hptep->v = 0;
> __tlbie(va, psize, ssize);
> }
> }
>
> - asm volatile("eieio; tlbsync; ptesync":::"memory");
> + asm volatile("eieio; tlbsync; ptesync": : :"memory");
> spin_unlock(&native_tlbie_lock);
> local_irq_restore(flags);
> }
>
> /*
> @@ -495,38 +495,38 @@
> } pte_iterate_hashed_end();
> }
>
> if (cpu_has_feature(CPU_FTR_TLBIEL) &&
> mmu_psize_defs[psize].tlbiel && local) {
> - asm volatile("ptesync":::"memory");
> + asm volatile("ptesync": : :"memory");
> for (i = 0; i < number; i++) {
> va = batch->vaddr[i];
> pte = batch->pte[i];
>
> pte_iterate_hashed_subpages(pte, psize, va, index,
> shift) {
> __tlbiel(va, psize, ssize);
> } pte_iterate_hashed_end();
> }
> - asm volatile("ptesync":::"memory");
> + asm volatile("ptesync": : :"memory");
> } else {
> int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE);
>
> if (lock_tlbie)
> spin_lock(&native_tlbie_lock);
>
> - asm volatile("ptesync":::"memory");
> + asm volatile("ptesync": : :"memory");
> for (i = 0; i < number; i++) {
> va = batch->vaddr[i];
> pte = batch->pte[i];
>
> pte_iterate_hashed_subpages(pte, psize, va, index,
> shift) {
> __tlbie(va, psize, ssize);
> } pte_iterate_hashed_end();
> }
> - asm volatile("eieio; tlbsync; ptesync":::"memory");
> + asm volatile("eieio; tlbsync; ptesync": : :"memory");
>
> if (lock_tlbie)
> spin_unlock(&native_tlbie_lock);
> }
>
> diff -U 5 -r linux-2.6.24.7/arch/powerpc/mm/slb.c
> linux-2.6.24.7-patched/arch/powerpc/mm/slb.c
> --- linux-2.6.24.7/arch/powerpc/mm/slb.c 2008-11-18
> 17:36:05.000000000 -0600
> +++ linux-2.6.24.7-patched/arch/powerpc/mm/slb.c 2008-11-19
> 16:47:17.000000000 -0600
> @@ -299,7 +299,7 @@
>
> /* We don't bolt the stack for the time being - we're in boot,
> * so the stack is in the bolted segment. By the time it goes
> * elsewhere, we'll call _switch() which will bolt in the new
> * one. */
> - asm volatile("isync":::"memory");
> + asm volatile("isync": : :"memory");
> }
> Only in linux-2.6.24.7-patched/arch/powerpc/mm: slb.c.orig
> diff -U 5 -r linux-2.6.24.7/arch/powerpc/mm/stab.c
> linux-2.6.24.7-patched/arch/powerpc/mm/stab.c
> --- linux-2.6.24.7/arch/powerpc/mm/stab.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/powerpc/mm/stab.c 2008-11-19
> 16:47:17.000000000 -0600
> @@ -140,11 +140,11 @@
> else
> offset = NR_STAB_CACHE_ENTRIES+1;
> __get_cpu_var(stab_cache_ptr) = offset;
>
> /* Order update */
> - asm volatile("sync":::"memory");
> + asm volatile("sync": : :"memory");
> }
>
> return 0;
> }
>
> @@ -194,11 +194,11 @@
> ste->esid_data = 0;
> }
> }
> }
>
> - asm volatile("sync; slbia; sync":::"memory");
> + asm volatile("sync; slbia; sync": : :"memory");
>
> __get_cpu_var(stab_cache_ptr) = 0;
>
> /* Now preload some entries for the new task */
> if (test_tsk_thread_flag(tsk, TIF_32BIT))
> @@ -263,15 +263,15 @@
> void stab_initialize(unsigned long stab)
> {
> unsigned long vsid = get_kernel_vsid(PAGE_OFFSET, MMU_SEGSIZE_256M);
> unsigned long stabreal;
>
> - asm volatile("isync; slbia; isync":::"memory");
> + asm volatile("isync; slbia; isync": : :"memory");
> make_ste(stab, GET_ESID(PAGE_OFFSET), vsid);
>
> /* Order update */
> - asm volatile("sync":::"memory");
> + asm volatile("sync": : :"memory");
>
> /* Set ASR */
> stabreal = get_paca()->stab_real | 0x1ul;
>
> #ifdef CONFIG_PPC_ISERIES
> diff -U 5 -r linux-2.6.24.7/arch/powerpc/platforms/celleb/scc_epci.c
> linux-2.6.24.7-patched/arch/powerpc/platforms/celleb/scc_epci.c
> --- linux-2.6.24.7/arch/powerpc/platforms/celleb/scc_epci.c 2008-11-18
> 17:36:05.000000000 -0600
> +++ linux-2.6.24.7-patched/arch/powerpc/platforms/celleb/scc_epci.c
> 2008-11-19 16:47:17.000000000 -0600
> @@ -39,11 +39,11 @@
> #include "interrupt.h"
>
> #define MAX_PCI_DEVICES 32
> #define MAX_PCI_FUNCTIONS 8
>
> -#define iob() __asm__ __volatile__("eieio; sync":::"memory")
> +#define iob() __asm__ __volatile__("eieio; sync": : :"memory")
>
> struct epci_private {
> dma_addr_t dummy_page_da;
> };
>
> diff -U 5 -r linux-2.6.24.7/arch/powerpc/platforms/chrp/smp.c
> linux-2.6.24.7-patched/arch/powerpc/platforms/chrp/smp.c
> --- linux-2.6.24.7/arch/powerpc/platforms/chrp/smp.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/powerpc/platforms/chrp/smp.c 2008-11-19
> 16:47:17.000000000 -0600
> @@ -32,11 +32,11 @@
> #include <asm/rtas.h>
>
> static void __devinit smp_chrp_kick_cpu(int nr)
> {
> *(unsigned long *)KERNELBASE = nr;
> - asm volatile("dcbf 0,%0"::"r"(KERNELBASE):"memory");
> + asm volatile("dcbf 0,%0": :"r"(KERNELBASE):"memory");
> }
>
> static void __devinit smp_chrp_setup_cpu(int cpu_nr)
> {
> mpic_setup_this_cpu();
> diff -U 5 -r linux-2.6.24.7/arch/ppc/kernel/smp-tbsync.c
> linux-2.6.24.7-patched/arch/ppc/kernel/smp-tbsync.c
> --- linux-2.6.24.7/arch/ppc/kernel/smp-tbsync.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/ppc/kernel/smp-tbsync.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -68,12 +68,12 @@
> break;
>
> if( cmd == kSetAndTest ) {
> while( tbsync->handshake )
> ;
> - asm volatile ("mttbl %0" :: "r" (tbl) );
> - asm volatile ("mttbu %0" :: "r" (tbu) );
> + asm volatile ("mttbl %0" : : "r" (tbl) );
> + asm volatile ("mttbu %0" : : "r" (tbu) );
> } else {
> while( tbsync->handshake )
> ;
> }
> enter_contest( tbsync->mark, -1 );
> diff -U 5 -r linux-2.6.24.7/arch/ppc/platforms/ev64260.c
> linux-2.6.24.7-patched/arch/ppc/platforms/ev64260.c
> --- linux-2.6.24.7/arch/ppc/platforms/ev64260.c 2008-11-18
> 17:36:05.000000000 -0600
> +++ linux-2.6.24.7-patched/arch/ppc/platforms/ev64260.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -491,11 +491,11 @@
> __asm__ __volatile__
> ("mtspr 26, %0\n\t"
> "li 4,(1<<6)\n\t"
> "mtspr 27,4\n\t"
> "rfi\n\t"
> - :: "r" (addr):"r4");
> + : : "r" (addr):"r4");
>
> return;
> }
>
> static void
> diff -U 5 -r linux-2.6.24.7/arch/ppc/platforms/hdpu.c
> linux-2.6.24.7-patched/arch/ppc/platforms/hdpu.c
> --- linux-2.6.24.7/arch/ppc/platforms/hdpu.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/ppc/platforms/hdpu.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -439,11 +439,11 @@
> static void __init hdpu_set_l1pe()
> {
> unsigned long ictrl;
> asm volatile ("mfspr %0, 1011":"=r" (ictrl):);
> ictrl |= ICTRL_EICE | ICTRL_EDC | ICTRL_EICP;
> - asm volatile ("mtspr 1011, %0"::"r" (ictrl));
> + asm volatile ("mtspr 1011, %0": :"r" (ictrl));
> }
>
> /*
> * Set BAT 1 to map 0xf1000000 to end of physical memory space.
> */
> @@ -805,11 +805,11 @@
> * Wait 100mSecond until other CPU has reached __secondary_start.
> * When it reaches, it is permittable to rever the SRAM mapping
> etc...
> */
> mdelay(100);
> *(unsigned long *)KERNELBASE = nr;
> - asm volatile ("dcbf 0,%0"::"r" (KERNELBASE):"memory");
> + asm volatile ("dcbf 0,%0": :"r" (KERNELBASE):"memory");
>
> iounmap(bootaddr);
>
> /* Set up window for internal sram (256KByte insize) */
> bh.ci->disable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
> diff -U 5 -r linux-2.6.24.7/arch/ppc/platforms/pplus.c
> linux-2.6.24.7-patched/arch/ppc/platforms/pplus.c
> --- linux-2.6.24.7/arch/ppc/platforms/pplus.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/ppc/platforms/pplus.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -735,11 +735,11 @@
> }
>
> static void __init smp_pplus_kick_cpu(int nr)
> {
> *(unsigned long *)KERNELBASE = nr;
> - asm volatile ("dcbf 0,%0"::"r" (KERNELBASE):"memory");
> + asm volatile ("dcbf 0,%0": :"r" (KERNELBASE):"memory");
> printk(KERN_INFO "CPU1 reset, waiting\n");
> }
>
> static void __init smp_pplus_setup_cpu(int cpu_nr)
> {
> diff -U 5 -r linux-2.6.24.7/arch/ppc/platforms/prep_setup.c
> linux-2.6.24.7-patched/arch/ppc/platforms/prep_setup.c
> --- linux-2.6.24.7/arch/ppc/platforms/prep_setup.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/ppc/platforms/prep_setup.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -1025,11 +1025,11 @@
>
> static void __init
> smp_prep_kick_cpu(int nr)
> {
> *(unsigned long *)KERNELBASE = nr;
> - asm volatile("dcbf 0,%0"::"r"(KERNELBASE):"memory");
> + asm volatile("dcbf 0,%0": :"r"(KERNELBASE):"memory");
> printk("CPU1 released, waiting\n");
> }
>
> static void __init
> smp_prep_setup_cpu(int cpu_nr)
> diff -U 5 -r linux-2.6.24.7/arch/ppc/syslib/btext.c
> linux-2.6.24.7-patched/arch/ppc/syslib/btext.c
> --- linux-2.6.24.7/arch/ppc/syslib/btext.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/ppc/syslib/btext.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -271,11 +271,11 @@
> }
> }
>
> __inline__ void dcbst(const void* addr)
> {
> - __asm__ __volatile__ ("dcbst 0,%0" :: "r" (addr));
> + __asm__ __volatile__ ("dcbst 0,%0" : : "r" (addr));
> }
>
> void BTEXT btext_flushscreen(void)
> {
> boot_infos_t* bi = &disp_bi;
> diff -U 5 -r linux-2.6.24.7/arch/ppc/syslib/ibm440gx_common.c
> linux-2.6.24.7-patched/arch/ppc/syslib/ibm440gx_common.c
> --- linux-2.6.24.7/arch/ppc/syslib/ibm440gx_common.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/ppc/syslib/ibm440gx_common.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -153,11 +153,11 @@
> printk(KERN_ERR "Cannot install L2C error handler, cache is
> not enabled\n");
> return;
> }
>
> local_irq_save(flags);
> - asm volatile ("sync" ::: "memory");
> + asm volatile ("sync" : : : "memory");
>
> /* Disable SRAM */
> mtdcr(DCRN_SRAM0_DPC, mfdcr(DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE);
> mtdcr(DCRN_SRAM0_SB0CR, mfdcr(DCRN_SRAM0_SB0CR) &
> ~SRAM_SBCR_BU_MASK);
> mtdcr(DCRN_SRAM0_SB1CR, mfdcr(DCRN_SRAM0_SB1CR) &
> ~SRAM_SBCR_BU_MASK);
> @@ -185,31 +185,31 @@
>
> r = mfdcr(DCRN_L2C0_SNP1) & ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
> r |= 0x80000000 | L2C_SNP_SSR_32G | L2C_SNP_ESR;
> mtdcr(DCRN_L2C0_SNP1, r);
>
> - asm volatile ("sync" ::: "memory");
> + asm volatile ("sync" : : : "memory");
>
> /* Enable ICU/DCU ports */
> r = mfdcr(DCRN_L2C0_CFG);
> r &= ~(L2C_CFG_DCW_MASK | L2C_CFG_PMUX_MASK | L2C_CFG_PMIM |
> L2C_CFG_TPEI
> | L2C_CFG_CPEI | L2C_CFG_NAM | L2C_CFG_NBRM);
> r |= L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_TPC | L2C_CFG_CPC |
> L2C_CFG_FRAN
> | L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM | L2C_CFG_SMCM;
> mtdcr(DCRN_L2C0_CFG, r);
>
> - asm volatile ("sync; isync" ::: "memory");
> + asm volatile ("sync; isync" : : : "memory");
> local_irq_restore(flags);
> }
>
> /* Disable L2 cache */
> void __init ibm440gx_l2c_disable(void){
> u32 r;
> unsigned long flags;
>
> local_irq_save(flags);
> - asm volatile ("sync" ::: "memory");
> + asm volatile ("sync" : : : "memory");
>
> /* Disable L2C mode */
> r = mfdcr(DCRN_L2C0_CFG) & ~(L2C_CFG_L2M | L2C_CFG_ICU |
> L2C_CFG_DCU);
> mtdcr(DCRN_L2C0_CFG, r);
>
> @@ -222,11 +222,11 @@
> mtdcr(DCRN_SRAM0_SB2CR,
> SRAM_SBCR_BAS2 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW);
> mtdcr(DCRN_SRAM0_SB3CR,
> SRAM_SBCR_BAS3 | SRAM_SBCR_BS_64KB | SRAM_SBCR_BU_RW);
>
> - asm volatile ("sync; isync" ::: "memory");
> + asm volatile ("sync; isync" : : : "memory");
> local_irq_restore(flags);
> }
>
> void __init ibm440gx_l2c_setup(struct ibm44x_clocks* p)
> {
> diff -U 5 -r linux-2.6.24.7/arch/um/include/sysdep-x86_64/barrier.h
> linux-2.6.24.7-patched/arch/um/include/sysdep-x86_64/barrier.h
> --- linux-2.6.24.7/arch/um/include/sysdep-x86_64/barrier.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/um/include/sysdep-x86_64/barrier.h
> 2008-11-19 16:47:18.000000000 -0600
> @@ -1,7 +1,7 @@
> #ifndef __SYSDEP_X86_64_BARRIER_H
> #define __SYSDEP_X86_64_BARRIER_H
>
> /* Copied from include/asm-x86_64 for use by userspace. */
> -#define mb() asm volatile("mfence":::"memory")
> +#define mb() asm volatile("mfence": : :"memory")
>
> #endif
> diff -U 5 -r linux-2.6.24.7/arch/v850/kernel/highres_timer.c
> linux-2.6.24.7-patched/arch/v850/kernel/highres_timer.c
> --- linux-2.6.24.7/arch/v850/kernel/highres_timer.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/v850/kernel/highres_timer.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -32,11 +32,11 @@
> asm ("ld.w %0[r0], sp;"
> "add 1, sp;"
> "st.w sp, %0[r0];"
> "ld.w %1[r0], sp;" /* restore pre-irq stack-pointer */
> "reti"
> - ::
> + : :
> "i" (HIGHRES_TIMER_SLOW_TICKS_ADDR),
> "i" (ENTRY_SP_ADDR)
> : "memory");
> }
>
> diff -U 5 -r linux-2.6.24.7/arch/v850/kernel/process.c
> linux-2.6.24.7-patched/arch/v850/kernel/process.c
> --- linux-2.6.24.7/arch/v850/kernel/process.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/v850/kernel/process.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -36,11 +36,11 @@
>
> /* The idle loop. */
> static void default_idle (void)
> {
> while (! need_resched ())
> - asm ("halt; nop; nop; nop; nop; nop" ::: "cc");
> + asm ("halt; nop; nop; nop; nop; nop" : : : "cc");
> }
>
> void (*idle)(void) = default_idle;
>
> /*
> diff -U 5 -r linux-2.6.24.7/arch/v850/kernel/v850e_cache.c
> linux-2.6.24.7-patched/arch/v850/kernel/v850e_cache.c
> --- linux-2.6.24.7/arch/v850/kernel/v850e_cache.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/v850/kernel/v850e_cache.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -49,11 +49,11 @@
> #endif
> *r0_ram++ = 0xf06a3760; /* st.h r6, 0xfffff06a[r0] */
> *r0_ram = 0x5640006b; /* jmp [r11] */
>
> asm ("mov hilo(1f), r11; jmp [%1]; 1:;"
> - :: "r" (bhc_val), "r" (R0_RAM_ADDR) : "r11");
> + : : "r" (bhc_val), "r" (R0_RAM_ADDR) : "r11");
> }
>
> static void clear_icache (void)
> {
> /* 1. Read the instruction cache control register (ICC) and confirm
> diff -U 5 -r linux-2.6.24.7/arch/v850/lib/memcpy.c
> linux-2.6.24.7-patched/arch/v850/lib/memcpy.c
> --- linux-2.6.24.7/arch/v850/lib/memcpy.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/v850/lib/memcpy.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -30,11 +30,11 @@
> "mov %1, ep;" \
> "sst.w r1, 0[ep]; sst.w r12, 4[ep];" \
> "sst.w r13, 8[ep]; sst.w r14, 12[ep];" \
> "sst.w r15, 16[ep]; sst.w r17, 20[ep];" \
> "sst.w r18, 24[ep]; sst.w r19, 28[ep]" \
> - :: "r" (src), "r" (dst) \
> + : : "r" (src), "r" (dst) \
> : "r1", "r12", "r13", "r14", "r15", \
> "r17", "r18", "r19", "ep", "memory");
>
> void *memcpy (void *dst, const void *src, __kernel_size_t size)
> {
> diff -U 5 -r linux-2.6.24.7/arch/v850/lib/memset.c
> linux-2.6.24.7-patched/arch/v850/lib/memset.c
> --- linux-2.6.24.7/arch/v850/lib/memset.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/v850/lib/memset.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -40,11 +40,11 @@
> for (loop = count / 32; loop; loop--) {
> asm ("sst.w %0, 0[ep]; sst.w %0, 4[ep];"
> "sst.w %0, 8[ep]; sst.w %0, 12[ep];"
> "sst.w %0, 16[ep]; sst.w %0, 20[ep];"
> "sst.w %0, 24[ep]; sst.w %0, 28[ep]"
> - :: "r" (val) : "memory");
> + : : "r" (val) : "memory");
> ptr += 32;
> }
> count %= 32;
>
> /* long copying loop. */
> diff -U 5 -r linux-2.6.24.7/arch/v850/lib/negdi2.c
> linux-2.6.24.7-patched/arch/v850/lib/negdi2.c
> --- linux-2.6.24.7/arch/v850/lib/negdi2.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/v850/lib/negdi2.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -19,7 +19,7 @@
> ("not r6, r10;"
> "add 1, r10;"
> "setf c, r6;"
> "not r7, r11;"
> "add r6, r11"
> - ::: "r6", "r7", "r10", "r11");
> + : : : "r6", "r7", "r10", "r11");
> }
> diff -U 5 -r linux-2.6.24.7/arch/x86/ia32/ia32_aout.c
> linux-2.6.24.7-patched/arch/x86/ia32/ia32_aout.c
> --- linux-2.6.24.7/arch/x86/ia32/ia32_aout.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/x86/ia32/ia32_aout.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -410,11 +410,11 @@
> }
>
> current->mm->start_stack =
> (unsigned long)create_aout_tables((char __user *)bprm->p,
> bprm);
> /* start thread */
> - asm volatile("movl %0,%%fs" :: "r" (0)); \
> + asm volatile("movl %0,%%fs" : : "r" (0)); \
> asm volatile("movl %0,%%es; movl %0,%%ds": :"r" (__USER32_DS));
> load_gs_index(0);
> (regs)->rip = ex.a_entry;
> (regs)->rsp = current->mm->start_stack;
> (regs)->eflags = 0x200;
> diff -U 5 -r linux-2.6.24.7/arch/x86/ia32/ia32_binfmt.c
> linux-2.6.24.7-patched/arch/x86/ia32/ia32_binfmt.c
> --- linux-2.6.24.7/arch/x86/ia32/ia32_binfmt.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/x86/ia32/ia32_binfmt.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -201,11 +201,11 @@
> #undef ELF_PLAT_INIT
> #define ELF_PLAT_INIT(r, load_addr) elf32_init(r)
>
> #undef start_thread
> #define start_thread(regs,new_rip,new_rsp) do { \
> - asm volatile("movl %0,%%fs" :: "r" (0)); \
> + asm volatile("movl %0,%%fs" : : "r" (0)); \
> asm volatile("movl %0,%%es; movl %0,%%ds": :"r" (__USER32_DS)); \
> load_gs_index(0); \
> (regs)->rip = (new_rip); \
> (regs)->rsp = (new_rsp); \
> (regs)->eflags = 0x200; \
> diff -U 5 -r linux-2.6.24.7/arch/x86/ia32/ia32_signal.c
> linux-2.6.24.7-patched/arch/x86/ia32/ia32_signal.c
> --- linux-2.6.24.7/arch/x86/ia32/ia32_signal.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/x86/ia32/ia32_signal.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -485,12 +485,12 @@
> /* Make -mregparm=3 work */
> regs->rax = sig;
> regs->rdx = 0;
> regs->rcx = 0;
>
> - asm volatile("movl %0,%%ds" :: "r" (__USER32_DS));
> - asm volatile("movl %0,%%es" :: "r" (__USER32_DS));
> + asm volatile("movl %0,%%ds" : : "r" (__USER32_DS));
> + asm volatile("movl %0,%%es" : : "r" (__USER32_DS));
>
> regs->cs = __USER32_CS;
> regs->ss = __USER32_DS;
>
> set_fs(USER_DS);
> @@ -591,12 +591,12 @@
> /* Make -mregparm=3 work */
> regs->rax = sig;
> regs->rdx = (unsigned long) &frame->info;
> regs->rcx = (unsigned long) &frame->uc;
>
> - asm volatile("movl %0,%%ds" :: "r" (__USER32_DS));
> - asm volatile("movl %0,%%es" :: "r" (__USER32_DS));
> + asm volatile("movl %0,%%ds" : : "r" (__USER32_DS));
> + asm volatile("movl %0,%%es" : : "r" (__USER32_DS));
>
> regs->cs = __USER32_CS;
> regs->ss = __USER32_DS;
>
> set_fs(USER_DS);
> diff -U 5 -r linux-2.6.24.7/arch/x86/kernel/setup64.c
> linux-2.6.24.7-patched/arch/x86/kernel/setup64.c
> --- linux-2.6.24.7/arch/x86/kernel/setup64.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/x86/kernel/setup64.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -117,11 +117,11 @@
> void pda_init(int cpu)
> {
> struct x8664_pda *pda = cpu_pda(cpu);
>
> /* Setup up data that may be needed in __get_free_pages early */
> - asm volatile("movl %0,%%fs ; movl %0,%%gs" :: "r" (0));
> + asm volatile("movl %0,%%fs ; movl %0,%%gs" : : "r" (0));
> /* Memory clobbers used to order PDA accessed */
> mb();
> wrmsrl(MSR_GS_BASE, pda);
> mb();
>
> diff -U 5 -r linux-2.6.24.7/arch/x86/pci/pci.h
> linux-2.6.24.7-patched/arch/x86/pci/pci.h
> --- linux-2.6.24.7/arch/x86/pci/pci.h 2008-05-06 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/x86/pci/pci.h 2008-11-19
> 16:47:18.000000000 -0600
> @@ -128,17 +128,17 @@
> return val;
> }
>
> static inline void mmio_config_writeb(void __iomem *pos, u8 val)
> {
> - asm volatile("movb %%al,(%1)" :: "a" (val), "r" (pos) : "memory");
> + asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
> }
>
> static inline void mmio_config_writew(void __iomem *pos, u16 val)
> {
> - asm volatile("movw %%ax,(%1)" :: "a" (val), "r" (pos) : "memory");
> + asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
> }
>
> static inline void mmio_config_writel(void __iomem *pos, u32 val)
> {
> - asm volatile("movl %%eax,(%1)" :: "a" (val), "r" (pos) : "memory");
> + asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) :
> "memory");
> }
> diff -U 5 -r linux-2.6.24.7/arch/xtensa/kernel/platform.c
> linux-2.6.24.7-patched/arch/xtensa/kernel/platform.c
> --- linux-2.6.24.7/arch/xtensa/kernel/platform.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/arch/xtensa/kernel/platform.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -31,11 +31,11 @@
> _F(void, setup, (char** cmd), { });
> _F(void, init_irq, (void), { });
> _F(void, restart, (void), { while(1); });
> _F(void, halt, (void), { while(1); });
> _F(void, power_off, (void), { while(1); });
> -_F(void, idle, (void), { __asm__ __volatile__ ("waiti 0" ::: "memory");
> });
> +_F(void, idle, (void), { __asm__ __volatile__ ("waiti 0" : : : "memory");
> });
> _F(void, heartbeat, (void), { });
> _F(int, pcibios_fixup, (void), { return 0; });
> _F(int, get_rtc_time, (time_t* t), { return 0; });
> _F(int, set_rtc_time, (time_t t), { return 0; });
>
> diff -U 5 -r linux-2.6.24.7/drivers/infiniband/hw/ipath/ipath_kernel.h
> linux-2.6.24.7-patched/drivers/infiniband/hw/ipath/ipath_kernel.h
> --- linux-2.6.24.7/drivers/infiniband/hw/ipath/ipath_kernel.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/drivers/infiniband/hw/ipath/ipath_kernel.h
> 2008-11-19 16:47:18.000000000 -0600
> @@ -960,11 +960,11 @@
> /*
> * Flush write combining store buffers (if present) and perform a write
> * barrier.
> */
> #if defined(CONFIG_X86_64)
> -#define ipath_flush_wc() asm volatile("sfence" ::: "memory")
> +#define ipath_flush_wc() asm volatile("sfence" : : : "memory")
> #else
> #define ipath_flush_wc() wmb()
> #endif
>
> extern unsigned ipath_debug; /* debugging bit mask */
> diff -U 5 -r linux-2.6.24.7/drivers/input/joystick/iforce/iforce.h
> linux-2.6.24.7-patched/drivers/input/joystick/iforce/iforce.h
> --- linux-2.6.24.7/drivers/input/joystick/iforce/iforce.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/drivers/input/joystick/iforce/iforce.h
> 2008-11-19 16:47:18.000000000 -0600
> @@ -45,11 +45,11 @@
> #include <linux/ioport.h>
>
>
> #define IFORCE_MAX_LENGTH 16
>
> -/* iforce::bus */
> +/* iforce: :bus */
> #define IFORCE_232 1
> #define IFORCE_USB 2
>
> #define IFORCE_EFFECTS_MAX 32
>
> @@ -85,11 +85,11 @@
> #define FF_CMD_QUERY 0xff01
>
> /* Buffer for async write */
> #define XMIT_SIZE 256
> #define XMIT_INC(var, n) (var)+=n; (var)&= XMIT_SIZE -1
> -/* iforce::xmit_flags */
> +/* iforce: :xmit_flags */
> #define IFORCE_XMIT_RUNNING 0
> #define IFORCE_XMIT_AGAIN 1
>
> struct iforce_device {
> u16 idvendor;
> diff -U 5 -r linux-2.6.24.7/drivers/input/serio/i8042-ppcio.h
> linux-2.6.24.7-patched/drivers/input/serio/i8042-ppcio.h
> --- linux-2.6.24.7/drivers/input/serio/i8042-ppcio.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/drivers/input/serio/i8042-ppcio.h 2008-11-19
> 16:47:18.000000000 -0600
> @@ -75,11 +75,11 @@
> eieio();
>
> asm volatile("lis 7,0xff88 \n\
> lswi 6,7,0x8 \n\
> mr %0,6"
> - : "=r" (kbd_data) :: "6", "7");
> + : "=r" (kbd_data) : : "6", "7");
>
> __raw_writel(0x00000000, 0xff50000c);
> eieio();
>
> return (unsigned char)(kbd_data >> 24);
> @@ -97,11 +97,11 @@
>
> asm volatile("lis 7,0xff88 \n\
> ori 7,7,0x8 \n\
> lswi 6,7,0x8 \n\
> mr %0,6"
> - : "=r" (kbd_status) :: "6", "7");
> + : "=r" (kbd_status) : : "6", "7");
>
> __raw_writel(0x00000000, 0xff50000c);
> eieio();
>
> return (unsigned char)(kbd_status >> 24);
> diff -U 5 -r linux-2.6.24.7/drivers/input/tablet/gtco.c
> linux-2.6.24.7-patched/drivers/input/tablet/gtco.c
> --- linux-2.6.24.7/drivers/input/tablet/gtco.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/drivers/input/tablet/gtco.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -276,11 +276,11 @@
> if (data == 2)
> strcpy(globtype, "Variable");
> else if (data == 3)
> strcpy(globtype, "Var|Const");
>
> - dbg("::::: Saving Report: %d input #%d Max:
> 0x%X(%d) Min:0x%X(%d) of %d bits",
> + dbg(": : : : : Saving Report: %d input #%d
> Max: 0x%X(%d) Min:0x%X(%d) of %d bits",
> globalval[TAG_GLOB_REPORT_ID], inputnum,
> globalval[TAG_GLOB_LOG_MAX],
> globalval[TAG_GLOB_LOG_MAX],
> globalval[TAG_GLOB_LOG_MIN],
> globalval[TAG_GLOB_LOG_MIN],
> globalval[TAG_GLOB_REPORT_SZ] *
> globalval[TAG_GLOB_REPORT_CNT]);
>
> diff -U 5 -r linux-2.6.24.7/drivers/kvm/svm.c
> linux-2.6.24.7-patched/drivers/kvm/svm.c
> --- linux-2.6.24.7/drivers/kvm/svm.c 2008-05-06 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/drivers/kvm/svm.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -128,11 +128,11 @@
> asm volatile (SVM_STGI);
> }
>
> static inline void invlpga(unsigned long addr, u32 asid)
> {
> - asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
> + asm volatile (SVM_INVLPGA : : "a"(addr), "c"(asid));
> }
>
> static inline unsigned long kvm_read_cr2(void)
> {
> unsigned long cr2;
> @@ -141,11 +141,11 @@
> return cr2;
> }
>
> static inline void kvm_write_cr2(unsigned long val)
> {
> - asm volatile ("mov %0, %%cr2" :: "r" (val));
> + asm volatile ("mov %0, %%cr2" : : "r" (val));
> }
>
> static inline unsigned long read_dr6(void)
> {
> unsigned long dr6;
> @@ -154,11 +154,11 @@
> return dr6;
> }
>
> static inline void write_dr6(unsigned long val)
> {
> - asm volatile ("mov %0, %%dr6" :: "r" (val));
> + asm volatile ("mov %0, %%dr6" : : "r" (val));
> }
>
> static inline unsigned long read_dr7(void)
> {
> unsigned long dr7;
> @@ -167,11 +167,11 @@
> return dr7;
> }
>
> static inline void write_dr7(unsigned long val)
> {
> - asm volatile ("mov %0, %%dr7" :: "r" (val));
> + asm volatile ("mov %0, %%dr7" : : "r" (val));
> }
>
> static inline void force_new_asid(struct kvm_vcpu *vcpu)
> {
> to_svm(vcpu)->asid_generation--;
> diff -U 5 -r linux-2.6.24.7/drivers/md/raid6sse1.c
> linux-2.6.24.7-patched/drivers/md/raid6sse1.c
> --- linux-2.6.24.7/drivers/md/raid6sse1.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/drivers/md/raid6sse1.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -146,11 +146,11 @@
> asm volatile("movntq %%mm3,%0" : "=m" (p[d+8]));
> asm volatile("movntq %%mm4,%0" : "=m" (q[d]));
> asm volatile("movntq %%mm6,%0" : "=m" (q[d+8]));
> }
>
> - asm volatile("sfence" : :: "memory");
> + asm volatile("sfence" : : : "memory");
> kernel_fpu_end();
> }
>
> const struct raid6_calls raid6_sse1x2 = {
> raid6_sse12_gen_syndrome,
> diff -U 5 -r linux-2.6.24.7/drivers/md/raid6sse2.c
> linux-2.6.24.7-patched/drivers/md/raid6sse2.c
> --- linux-2.6.24.7/drivers/md/raid6sse2.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/drivers/md/raid6sse2.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -176,11 +176,11 @@
> p = dptr[z0+1]; /* XOR parity */
> q = dptr[z0+2]; /* RS syndrome */
>
> kernel_fpu_begin();
>
> - asm volatile("movdqa %0,%%xmm0" :: "m"
> (raid6_sse_constants.x1d[0]));
> + asm volatile("movdqa %0,%%xmm0" : : "m"
> (raid6_sse_constants.x1d[0]));
> asm volatile("pxor %xmm2,%xmm2"); /* P[0] */
> asm volatile("pxor %xmm3,%xmm3"); /* P[1] */
> asm volatile("pxor %xmm4,%xmm4"); /* Q[0] */
> asm volatile("pxor %xmm5,%xmm5"); /* Zero temp */
> asm volatile("pxor %xmm6,%xmm6"); /* Q[1] */
> @@ -193,12 +193,12 @@
> asm volatile("pxor %xmm15,%xmm15"); /* Zero temp */
>
> for ( d = 0 ; d < bytes ; d += 64 ) {
> for ( z = z0 ; z >= 0 ; z-- ) {
> /* The second prefetch seems to improve
> performance... */
> - asm volatile("prefetchnta %0" :: "m" (dptr[z][d]));
> - asm volatile("prefetchnta %0" :: "m"
> (dptr[z][d+32]));
> + asm volatile("prefetchnta %0" : : "m"
> (dptr[z][d]));
> + asm volatile("prefetchnta %0" : : "m"
> (dptr[z][d+32]));
> asm volatile("pcmpgtb %xmm4,%xmm5");
> asm volatile("pcmpgtb %xmm6,%xmm7");
> asm volatile("pcmpgtb %xmm12,%xmm13");
> asm volatile("pcmpgtb %xmm14,%xmm15");
> asm volatile("paddb %xmm4,%xmm4");
> @@ -211,14 +211,14 @@
> asm volatile("pand %xmm0,%xmm15");
> asm volatile("pxor %xmm5,%xmm4");
> asm volatile("pxor %xmm7,%xmm6");
> asm volatile("pxor %xmm13,%xmm12");
> asm volatile("pxor %xmm15,%xmm14");
> - asm volatile("movdqa %0,%%xmm5" :: "m"
> (dptr[z][d]));
> - asm volatile("movdqa %0,%%xmm7" :: "m"
> (dptr[z][d+16]));
> - asm volatile("movdqa %0,%%xmm13" :: "m"
> (dptr[z][d+32]));
> - asm volatile("movdqa %0,%%xmm15" :: "m"
> (dptr[z][d+48]));
> + asm volatile("movdqa %0,%%xmm5" : : "m"
> (dptr[z][d]));
> + asm volatile("movdqa %0,%%xmm7" : : "m"
> (dptr[z][d+16]));
> + asm volatile("movdqa %0,%%xmm13" : : "m"
> (dptr[z][d+32]));
> + asm volatile("movdqa %0,%%xmm15" : : "m"
> (dptr[z][d+48]));
> asm volatile("pxor %xmm5,%xmm2");
> asm volatile("pxor %xmm7,%xmm3");
> asm volatile("pxor %xmm13,%xmm10");
> asm volatile("pxor %xmm15,%xmm11");
> asm volatile("pxor %xmm5,%xmm4");
> diff -U 5 -r linux-2.6.24.7/drivers/message/fusion/mptlan.c
> linux-2.6.24.7-patched/drivers/message/fusion/mptlan.c
> --- linux-2.6.24.7/drivers/message/fusion/mptlan.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/drivers/message/fusion/mptlan.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -194,11 +194,11 @@
> tmsg));
>
> switch (GET_LAN_FORM(tmsg)) {
>
> // NOTE! (Optimization) First case here is now caught in
> - // mptbase.c::mpt_interrupt() routine and callcack here
> + // mptbase.c: :mpt_interrupt() routine and callcack here
> // is now skipped for this case!
> #if 0
> case LAN_REPLY_FORM_MESSAGE_CONTEXT:
> // dioprintk((KERN_INFO MYNAM "/lan_reply: "
> // "MessageContext turbo reply
> received\n"));
> diff -U 5 -r linux-2.6.24.7/drivers/mtd/nand/cmx270_nand.c
> linux-2.6.24.7-patched/drivers/mtd/nand/cmx270_nand.c
> --- linux-2.6.24.7/drivers/mtd/nand/cmx270_nand.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/drivers/mtd/nand/cmx270_nand.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -38,11 +38,11 @@
> * unnecessary here and it cannot be used in module
> */
> #define DRAIN_WB() \
> do { \
> unsigned char dummy; \
> - asm volatile ("mcr p15, 0, r0, c7, c10, 4":::"r0"); \
> + asm volatile ("mcr p15, 0, r0, c7, c10, 4": : :"r0"); \
> dummy=*((unsigned char*)UNCACHED_ADDR); \
> } while(0)
>
> /* MTD structure for CM-X270 board */
> static struct mtd_info *cmx270_nand_mtd;
> diff -U 5 -r linux-2.6.24.7/drivers/net/ioc3-eth.c
> linux-2.6.24.7-patched/drivers/net/ioc3-eth.c
> --- linux-2.6.24.7/drivers/net/ioc3-eth.c 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/drivers/net/ioc3-eth.c 2008-11-19
> 16:47:18.000000000 -0600
> @@ -156,11 +156,11 @@
> #define RX_OFFSET 10
> #define RX_BUF_ALLOC_SIZE (1664 + RX_OFFSET + IOC3_CACHELINE)
>
> /* DMA barrier to separate cached and uncached accesses. */
> #define BARRIER() \
> - __asm__("sync" ::: "memory")
> + __asm__("sync" : : : "memory")
>
>
> #define IOC3_SIZE 0x100000
>
> /*
> diff -U 5 -r linux-2.6.24.7/drivers/net/wireless/hostap/hostap_hw.c
> linux-2.6.24.7-patched/drivers/net/wireless/hostap/hostap_hw.c
> --- linux-2.6.24.7/drivers/net/wireless/hostap/hostap_hw.c 2008-11-18
> 17:36:06.000000000 -0600
> +++ linux-2.6.24.7-patched/drivers/net/wireless/hostap/hostap_hw.c
> 2008-11-19 16:47:18.000000000 -0600
> @@ -1981,11 +1981,11 @@
> hdr_len = sizeof(rxdesc);
> status = le16_to_cpu(rxdesc.status);
> macport = (status >> 8) & 0x07;
>
> /* Drop frames with too large reported payload length. Monitor mode
> - * seems to sometimes pass frames (e.g., ctrl::ack) with signed and
> + * seems to sometimes pass frames (e.g., ctrl: :ack) with signed
> and
> * negative value, so allow also values 65522 .. 65534 (-14 .. -2)
> for
> * macport 7 */
> if (len > PRISM2_DATA_MAXLEN + 8 /* WEP */) {
> if (macport == 7 && local->iw_mode == IW_MODE_MONITOR) {
> if (len >= (u16) -14) {
> @@ -2395,11 +2395,11 @@
> status & HFA384X_TX_STATUS_FORMERR ? "[FormErr]" : "",
> le16_to_cpu(txdesc.tx_control));
>
> fc = le16_to_cpu(txdesc.frame_control);
> PDEBUG(DEBUG_EXTRA, " retry_count=%d tx_rate=%d fc=0x%04x "
> - "(%s%s%s::%d%s%s)\n",
> + "(%s%s%s: :%d%s%s)\n",
> txdesc.retry_count, txdesc.tx_rate, fc,
> WLAN_FC_GET_TYPE(fc) == IEEE80211_FTYPE_MGMT ? "Mgmt" : "",
> WLAN_FC_GET_TYPE(fc) == IEEE80211_FTYPE_CTL ? "Ctrl" : "",
> WLAN_FC_GET_TYPE(fc) == IEEE80211_FTYPE_DATA ? "Data" : "",
> WLAN_FC_GET_STYPE(fc) >> 4,
> Only in linux-2.6.24.7-patched/drivers/net/wireless/hostap:
> hostap_hw.c.orig
> diff -U 5 -r linux-2.6.24.7/drivers/net/wireless/rayctl.h
> linux-2.6.24.7-patched/drivers/net/wireless/rayctl.h
> --- linux-2.6.24.7/drivers/net/wireless/rayctl.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/drivers/net/wireless/rayctl.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -416,13 +416,11 @@
> short rx_hec_error; /* ECF incs on mac header CRC
> error */
> UCHAR rxnoise; /* Average RSL measurement
> */
> };
>
> /****** Host-to-ECF Data Area at Shared RAM offset 0x200
> *********************/
> -struct host_to_ecf_area {
> -
> -};
> +EMPTY_STRUCT_DECL(host_to_ecf_area);
>
> /****** ECF-to-Host Data Area at Shared RAM offset 0x0300
> ********************/
> struct startup_res_518 {
> UCHAR startup_word;
> UCHAR station_addr[ADDRLEN];
> diff -U 5 -r linux-2.6.24.7/drivers/video/i810/i810_main.h
> linux-2.6.24.7-patched/drivers/video/i810/i810_main.h
> --- linux-2.6.24.7/drivers/video/i810/i810_main.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/drivers/video/i810/i810_main.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -52,11 +52,11 @@
>
> /* Conditionals */
> #ifdef CONFIG_X86
> static inline void flush_cache(void)
> {
> - asm volatile ("wbinvd":::"memory");
> + asm volatile ("wbinvd": : :"memory");
> }
> #else
> #define flush_cache() do { } while(0)
> #endif
>
> diff -U 5 -r linux-2.6.24.7/fs/file_table.c
> linux-2.6.24.7-patched/fs/file_table.c
> --- linux-2.6.24.7/fs/file_table.c 2008-05-06 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/fs/file_table.c 2008-11-19
> 16:47:19.000000000 -0600
> @@ -28,10 +28,11 @@
> .max_files = NR_FILE
> };
>
> /* public. Not pretty! */
> __cacheline_aligned_in_smp DEFINE_SPINLOCK(files_lock);
> +EXPORT_SYMBOL(files_lock);
>
> static struct percpu_counter nr_files __cacheline_aligned_in_smp;
>
> static inline void file_free_rcu(struct rcu_head *head)
> {
> diff -U 5 -r linux-2.6.24.7/fs/super.c linux-2.6.24.7-patched/fs/super.c
> --- linux-2.6.24.7/fs/super.c 2008-05-06 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/fs/super.c 2008-11-19 16:47:19.000000000 -0600
> @@ -41,10 +41,12 @@
>
>
> LIST_HEAD(super_blocks);
> DEFINE_SPINLOCK(sb_lock);
>
> +EXPORT_SYMBOL(sb_lock);
> +
> /**
> * alloc_super - create new superblock
> * @type: filesystem type superblock should belong to
> *
> * Allocates and initializes a new &struct super_block. alloc_super()
> Only in linux-2.6.24.7/include: asm
> diff -U 5 -r linux-2.6.24.7/include/asm-alpha/core_tsunami.h
> linux-2.6.24.7-patched/include/asm-alpha/core_tsunami.h
> --- linux-2.6.24.7/include/asm-alpha/core_tsunami.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-alpha/core_tsunami.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -280,12 +280,11 @@
> #define TSUNAMI_DAC_OFFSET (1UL << 40)
>
> /*
> * Data structure for handling TSUNAMI machine checks:
> */
> -struct el_TSUNAMI_sysdata_mcheck {
> -};
> +EMPTY_STRUCT_DECL(el_TSUNAMI_sysdata_mcheck);
>
>
> #ifdef __KERNEL__
>
> #ifndef __EXTERN_INLINE
> diff -U 5 -r linux-2.6.24.7/include/asm-alpha/processor.h
> linux-2.6.24.7-patched/include/asm-alpha/processor.h
> --- linux-2.6.24.7/include/asm-alpha/processor.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-alpha/processor.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -29,12 +29,12 @@
> typedef struct {
> unsigned long seg;
> } mm_segment_t;
>
> /* This is dead. Everything has been moved to thread_info. */
> -struct thread_struct { };
> -#define INIT_THREAD { }
> +EMPTY_STRUCT_DECL(thread_struct);
> +#define INIT_THREAD EMPTY_STRUCT_INIT(thread_struct)
>
> /* Return saved PC of a blocked thread. */
> struct task_struct;
> extern unsigned long thread_saved_pc(struct task_struct *);
>
> diff -U 5 -r linux-2.6.24.7/include/asm-alpha/system.h
> linux-2.6.24.7-patched/include/asm-alpha/system.h
> --- linux-2.6.24.7/include/asm-alpha/system.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-alpha/system.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -551,11 +551,11 @@
> */
>
> #define __HAVE_ARCH_CMPXCHG 1
>
> static inline unsigned long
> -__cmpxchg_u8(volatile char *m, long old, long new)
> +__cmpxchg_u8(volatile char *m, long old, long n)
> {
> unsigned long prev, tmp, cmp, addr64;
>
> __asm__ __volatile__(
> " andnot %5,7,%4\n"
> @@ -573,18 +573,18 @@
> #endif
> "2:\n"
> ".subsection 2\n"
> "3: br 1b\n"
> ".previous"
> - : "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r"
> (addr64)
> - : "r" ((long)m), "Ir" (old), "1" (new) : "memory");
> + : "=&r" (prev), "=&r" (n), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64)
> + : "r" ((long)m), "Ir" (old), "1" (n) : "memory");
>
> return prev;
> }
>
> static inline unsigned long
> -__cmpxchg_u16(volatile short *m, long old, long new)
> +__cmpxchg_u16(volatile short *m, long old, long n)
> {
> unsigned long prev, tmp, cmp, addr64;
>
> __asm__ __volatile__(
> " andnot %5,7,%4\n"
> @@ -602,18 +602,18 @@
> #endif
> "2:\n"
> ".subsection 2\n"
> "3: br 1b\n"
> ".previous"
> - : "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r"
> (addr64)
> - : "r" ((long)m), "Ir" (old), "1" (new) : "memory");
> + : "=&r" (prev), "=&r" (n), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64)
> + : "r" ((long)m), "Ir" (old), "1" (n) : "memory");
>
> return prev;
> }
>
> static inline unsigned long
> -__cmpxchg_u32(volatile int *m, int old, int new)
> +__cmpxchg_u32(volatile int *m, int old, int n)
> {
> unsigned long prev, cmp;
>
> __asm__ __volatile__(
> "1: ldl_l %0,%5\n"
> @@ -628,17 +628,17 @@
> "2:\n"
> ".subsection 2\n"
> "3: br 1b\n"
> ".previous"
> : "=&r"(prev), "=&r"(cmp), "=m"(*m)
> - : "r"((long) old), "r"(new), "m"(*m) : "memory");
> + : "r"((long) old), "r"(n), "m"(*m) : "memory");
>
> return prev;
> }
>
> static inline unsigned long
> -__cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
> +__cmpxchg_u64(volatile long *m, unsigned long old, unsigned long n)
> {
> unsigned long prev, cmp;
>
> __asm__ __volatile__(
> "1: ldq_l %0,%5\n"
> @@ -653,31 +653,31 @@
> "2:\n"
> ".subsection 2\n"
> "3: br 1b\n"
> ".previous"
> : "=&r"(prev), "=&r"(cmp), "=m"(*m)
> - : "r"((long) old), "r"(new), "m"(*m) : "memory");
> + : "r"((long) old), "r"(n), "m"(*m) : "memory");
>
> return prev;
> }
>
> /* This function doesn't exist, so you'll get a linker error
> if something tries to do an invalid cmpxchg(). */
> extern void __cmpxchg_called_with_bad_pointer(void);
>
> static __always_inline unsigned long
> -__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int
> size)
> +__cmpxchg(volatile void *ptr, unsigned long old, unsigned long n, int
> size)
> {
> switch (size) {
> case 1:
> - return __cmpxchg_u8(ptr, old, new);
> + return __cmpxchg_u8(ptr, old, n);
> case 2:
> - return __cmpxchg_u16(ptr, old, new);
> + return __cmpxchg_u16(ptr, old, n);
> case 4:
> - return __cmpxchg_u32(ptr, old, new);
> + return __cmpxchg_u32(ptr, old, n);
> case 8:
> - return __cmpxchg_u64(ptr, old, new);
> + return __cmpxchg_u64(ptr, old, n);
> }
> __cmpxchg_called_with_bad_pointer();
> return old;
> }
>
> @@ -688,11 +688,11 @@
> (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
> (unsigned long)_n_, sizeof(*(ptr))); \
> })
>
> static inline unsigned long
> -__cmpxchg_u8_local(volatile char *m, long old, long new)
> +__cmpxchg_u8_local(volatile char *m, long old, long n)
> {
> unsigned long prev, tmp, cmp, addr64;
>
> __asm__ __volatile__(
> " andnot %5,7,%4\n"
> @@ -707,18 +707,18 @@
> " beq %2,3f\n"
> "2:\n"
> ".subsection 2\n"
> "3: br 1b\n"
> ".previous"
> - : "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r"
> (addr64)
> - : "r" ((long)m), "Ir" (old), "1" (new) : "memory");
> + : "=&r" (prev), "=&r" (n), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64)
> + : "r" ((long)m), "Ir" (old), "1" (n) : "memory");
>
> return prev;
> }
>
> static inline unsigned long
> -__cmpxchg_u16_local(volatile short *m, long old, long new)
> +__cmpxchg_u16_local(volatile short *m, long old, long n)
> {
> unsigned long prev, tmp, cmp, addr64;
>
> __asm__ __volatile__(
> " andnot %5,7,%4\n"
> @@ -733,18 +733,18 @@
> " beq %2,3f\n"
> "2:\n"
> ".subsection 2\n"
> "3: br 1b\n"
> ".previous"
> - : "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r"
> (addr64)
> - : "r" ((long)m), "Ir" (old), "1" (new) : "memory");
> + : "=&r" (prev), "=&r" (n), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64)
> + : "r" ((long)m), "Ir" (old), "1" (n) : "memory");
>
> return prev;
> }
>
> static inline unsigned long
> -__cmpxchg_u32_local(volatile int *m, int old, int new)
> +__cmpxchg_u32_local(volatile int *m, int old, int n)
> {
> unsigned long prev, cmp;
>
> __asm__ __volatile__(
> "1: ldl_l %0,%5\n"
> @@ -756,17 +756,17 @@
> "2:\n"
> ".subsection 2\n"
> "3: br 1b\n"
> ".previous"
> : "=&r"(prev), "=&r"(cmp), "=m"(*m)
> - : "r"((long) old), "r"(new), "m"(*m) : "memory");
> + : "r"((long) old), "r"(n), "m"(*m) : "memory");
>
> return prev;
> }
>
> static inline unsigned long
> -__cmpxchg_u64_local(volatile long *m, unsigned long old, unsigned long
> new)
> +__cmpxchg_u64_local(volatile long *m, unsigned long old, unsigned long n)
> {
> unsigned long prev, cmp;
>
> __asm__ __volatile__(
> "1: ldq_l %0,%5\n"
> @@ -778,28 +778,28 @@
> "2:\n"
> ".subsection 2\n"
> "3: br 1b\n"
> ".previous"
> : "=&r"(prev), "=&r"(cmp), "=m"(*m)
> - : "r"((long) old), "r"(new), "m"(*m) : "memory");
> + : "r"((long) old), "r"(n), "m"(*m) : "memory");
>
> return prev;
> }
>
> static __always_inline unsigned long
> -__cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
> +__cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long n,
> int size)
> {
> switch (size) {
> case 1:
> - return __cmpxchg_u8_local(ptr, old, new);
> + return __cmpxchg_u8_local(ptr, old, n);
> case 2:
> - return __cmpxchg_u16_local(ptr, old, new);
> + return __cmpxchg_u16_local(ptr, old, n);
> case 4:
> - return __cmpxchg_u32_local(ptr, old, new);
> + return __cmpxchg_u32_local(ptr, old, n);
> case 8:
> - return __cmpxchg_u64_local(ptr, old, new);
> + return __cmpxchg_u64_local(ptr, old, n);
> }
> __cmpxchg_called_with_bad_pointer();
> return old;
> }
>
> diff -U 5 -r linux-2.6.24.7/include/asm-arm/arch-iop13xx/iop13xx.h
> linux-2.6.24.7-patched/include/asm-arm/arch-iop13xx/iop13xx.h
> --- linux-2.6.24.7/include/asm-arm/arch-iop13xx/iop13xx.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-arm/arch-iop13xx/iop13xx.h
> 2008-11-19 16:47:19.000000000 -0600
> @@ -26,11 +26,11 @@
> asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
> return val;
> }
> static inline void write_wdtcr(u32 val)
> {
> - asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
> + asm volatile("mcr p6, 0, %0, c7, c9, 0": :"r" (val));
> }
>
> /* WDTSR CP6 R8 Page 9 */
> static inline u32 read_wdtsr(void)
> {
> @@ -38,11 +38,11 @@
> asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
> return val;
> }
> static inline void write_wdtsr(u32 val)
> {
> - asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
> + asm volatile("mcr p6, 0, %0, c8, c9, 0": :"r" (val));
> }
>
> /* RCSR - Reset Cause Status Register */
> static inline u32 read_rcsr(void)
> {
> diff -U 5 -r linux-2.6.24.7/include/asm-arm/arch-omap/mtd-xip.h
> linux-2.6.24.7-patched/include/asm-arm/arch-omap/mtd-xip.h
> --- linux-2.6.24.7/include/asm-arm/arch-omap/mtd-xip.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-arm/arch-omap/mtd-xip.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -54,8 +54,8 @@
> * the system timer tick period. This should put the CPU into idle mode
> * to save power and to be woken up only when some interrupts are pending.
> * As above, this should not rely upon standard kernel code.
> */
>
> -#define xip_cpu_idle() asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r"
> (1))
> +#define xip_cpu_idle() asm volatile ("mcr p15, 0, %0, c7, c0, 4" : : "r"
> (1))
>
> #endif /* __ARCH_OMAP_MTD_XIP_H__ */
> diff -U 5 -r linux-2.6.24.7/include/asm-arm/arch-pxa/mtd-xip.h
> linux-2.6.24.7-patched/include/asm-arm/arch-pxa/mtd-xip.h
> --- linux-2.6.24.7/include/asm-arm/arch-pxa/mtd-xip.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-arm/arch-pxa/mtd-xip.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -30,8 +30,8 @@
> * the system timer tick period. This should put the CPU into idle mode
> * to save power and to be woken up only when some interrupts are pending.
> * As above, this should not rely upon standard kernel code.
> */
>
> -#define xip_cpu_idle() asm volatile ("mcr p14, 0, %0, c7, c0, 0" :: "r"
> (1))
> +#define xip_cpu_idle() asm volatile ("mcr p14, 0, %0, c7, c0, 0" : : "r"
> (1))
>
> #endif /* __ARCH_PXA_MTD_XIP_H__ */
> diff -U 5 -r linux-2.6.24.7/include/asm-arm/hardware/iop3xx.h
> linux-2.6.24.7-patched/include/asm-arm/hardware/iop3xx.h
> --- linux-2.6.24.7/include/asm-arm/hardware/iop3xx.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-arm/hardware/iop3xx.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -287,11 +287,11 @@
> asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val));
> return val;
> }
> static inline void write_wdtcr(u32 val)
> {
> - asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val));
> + asm volatile("mcr p6, 0, %0, c7, c1, 0": :"r" (val));
> }
>
> extern unsigned long get_iop_tick_rate(void);
>
> /* only iop13xx has these registers, we define these to present a
> diff -U 5 -r linux-2.6.24.7/include/asm-arm/system.h
> linux-2.6.24.7-patched/include/asm-arm/system.h
> --- linux-2.6.24.7/include/asm-arm/system.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-arm/system.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -115,12 +115,12 @@
> int sig, const char *name);
>
> #define xchg(ptr,x) \
> ((__typeof__(*(ptr)))__xchg((unsigned
> long)(x),(ptr),sizeof(*(ptr))))
>
> -extern asmlinkage void __backtrace(void);
> -extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
> +asmlinkage void __backtrace(void);
> +asmlinkage void c_backtrace(unsigned long fp, int pmode);
>
> struct mm_struct;
> extern void show_pte(struct mm_struct *mm, unsigned long addr);
> extern void __show_regs(struct pt_regs *);
>
> diff -U 5 -r linux-2.6.24.7/include/asm-avr32/user.h
> linux-2.6.24.7-patched/include/asm-avr32/user.h
> --- linux-2.6.24.7/include/asm-avr32/user.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-avr32/user.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -36,13 +36,12 @@
> * backtrace. We need to write the data from usp to
> * current->start_stack, so we round each of these in order to be able
> * to write an integer number of pages.
> */
>
> -struct user_fpu_struct {
> - /* We have no FPU (yet) */
> -};
> +EMPTY_STRUCT_DECL(user_fpu_struct);
> +/* We have no FPU (yet) */
>
> struct user {
> struct pt_regs regs; /* entire machine state */
> size_t u_tsize; /* text size (pages) */
> size_t u_dsize; /* data size (pages) */
> diff -U 5 -r linux-2.6.24.7/include/asm-blackfin/processor.h
> linux-2.6.24.7-patched/include/asm-blackfin/processor.h
> --- linux-2.6.24.7/include/asm-blackfin/processor.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-blackfin/processor.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -19,11 +19,11 @@
> return usp;
> }
>
> static inline void wrusp(unsigned long usp)
> {
> - __asm__ __volatile__("usp = %0;\n\t"::"da"(usp));
> + __asm__ __volatile__("usp = %0;\n\t": :"da"(usp));
> }
>
> /*
> * User space process size: 1st byte beyond user address space.
> */
> diff -U 5 -r linux-2.6.24.7/include/asm-blackfin/system.h
> linux-2.6.24.7-patched/include/asm-blackfin/system.h
> --- linux-2.6.24.7/include/asm-blackfin/system.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-blackfin/system.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -122,11 +122,11 @@
> })
>
> /*
> * Force strict CPU ordering.
> */
> -#define nop() asm volatile ("nop;\n\t"::)
> +#define nop() asm volatile ("nop;\n\t": :)
> #define mb() asm volatile ("" : : :"memory")
> #define rmb() asm volatile ("" : : :"memory")
> #define wmb() asm volatile ("" : : :"memory")
> #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
>
> diff -U 5 -r linux-2.6.24.7/include/asm-cris/arch-v10/io.h
> linux-2.6.24.7-patched/include/asm-cris/arch-v10/io.h
> --- linux-2.6.24.7/include/asm-cris/arch-v10/io.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-cris/arch-v10/io.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -182,12 +182,12 @@
> : : "rm" (s), "rm" (len) : "r9","r10","r11","r12","memory")
> #define TRACE_ON() __extension__ \
> ({ int _Foofoo; __asm__ volatile ("bmod [%0],%0" : "=r" (_Foofoo) : "0" \
> (255)); _Foofoo; })
>
> -#define TRACE_OFF() do { __asm__ volatile ("bmod [%0],%0" :: "r" (254)); }
> while (0)
> -#define SIM_END() do { __asm__ volatile ("bmod [%0],%0" :: "r" (28)); }
> while (0)
> +#define TRACE_OFF() do { __asm__ volatile ("bmod [%0],%0" : : "r" (254));
> } while (0)
> +#define SIM_END() do { __asm__ volatile ("bmod [%0],%0" : : "r" (28)); }
> while (0)
> #define CRIS_CYCLES() __extension__ \
> ({ unsigned long c; asm ("bmod [%1],%0" : "=r" (c) : "r" (27)); c;})
> #endif /* ! defined CONFIG_SVINTO_SIM */
>
> #endif
> diff -U 5 -r linux-2.6.24.7/include/asm-cris/module.h
> linux-2.6.24.7-patched/include/asm-cris/module.h
> --- linux-2.6.24.7/include/asm-cris/module.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-cris/module.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -1,9 +1,9 @@
> #ifndef _ASM_CRIS_MODULE_H
> #define _ASM_CRIS_MODULE_H
> /* cris is simple */
> -struct mod_arch_specific { };
> +EMPTY_STRUCT_DECL(mod_arch_specific);
>
> #define Elf_Shdr Elf32_Shdr
> #define Elf_Sym Elf32_Sym
> #define Elf_Ehdr Elf32_Ehdr
> #endif /* _ASM_CRIS_MODULE_H */
> diff -U 5 -r linux-2.6.24.7/include/asm-frv/bug.h
> linux-2.6.24.7-patched/include/asm-frv/bug.h
> --- linux-2.6.24.7/include/asm-frv/bug.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-frv/bug.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -15,11 +15,11 @@
>
> #ifdef CONFIG_BUG
> /*
> * Tell the user there is some problem.
> */
> -extern asmlinkage void __debug_bug_trap(int signr);
> +asmlinkage void __debug_bug_trap(int signr);
>
> #ifdef CONFIG_NO_KERNEL_MSG
> #define _debug_bug_printk()
> #else
> extern void __debug_bug_printk(const char *file, unsigned line);
> diff -U 5 -r linux-2.6.24.7/include/asm-frv/fpu.h
> linux-2.6.24.7-patched/include/asm-frv/fpu.h
> --- linux-2.6.24.7/include/asm-frv/fpu.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-frv/fpu.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -4,8 +4,8 @@
>
> /*
> * MAX floating point unit state size (FSAVE/FRESTORE)
> */
>
> -#define kernel_fpu_end() do { asm volatile("bar":::"memory");
> preempt_enable(); } while(0)
> +#define kernel_fpu_end() do { asm volatile("bar": : :"memory");
> preempt_enable(); } while(0)
>
> #endif /* __ASM_FPU_H */
> diff -U 5 -r linux-2.6.24.7/include/asm-frv/gdb-stub.h
> linux-2.6.24.7-patched/include/asm-frv/gdb-stub.h
> --- linux-2.6.24.7/include/asm-frv/gdb-stub.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-frv/gdb-stub.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -85,18 +85,18 @@
> extern int gdbstub_rx_char(unsigned char *_ch, int nonblock);
> extern void gdbstub_tx_char(unsigned char ch);
> extern void gdbstub_tx_flush(void);
> extern void gdbstub_do_rx(void);
>
> -extern asmlinkage void __debug_stub_init_break(void);
> -extern asmlinkage void __break_hijack_kernel_event(void);
> -extern asmlinkage void __break_hijack_kernel_event_breaks_here(void);
> -extern asmlinkage void start_kernel(void);
> -
> -extern asmlinkage void gdbstub_rx_handler(void);
> -extern asmlinkage void gdbstub_rx_irq(void);
> -extern asmlinkage void gdbstub_intercept(void);
> +asmlinkage void __debug_stub_init_break(void);
> +asmlinkage void __break_hijack_kernel_event(void);
> +asmlinkage void __break_hijack_kernel_event_breaks_here(void);
> +asmlinkage void start_kernel(void);
> +
> +asmlinkage void gdbstub_rx_handler(void);
> +asmlinkage void gdbstub_rx_irq(void);
> +asmlinkage void gdbstub_intercept(void);
>
> extern uint32_t __entry_usertrap_table[];
> extern uint32_t __entry_kerneltrap_table[];
>
> extern volatile u8 gdbstub_rx_buffer[PAGE_SIZE];
> diff -U 5 -r linux-2.6.24.7/include/asm-frv/highmem.h
> linux-2.6.24.7-patched/include/asm-frv/highmem.h
> --- linux-2.6.24.7/include/asm-frv/highmem.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-frv/highmem.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -80,15 +80,15 @@
> unsigned long damlr, dampr;
> \
>
> \
> dampr = paddr | xAMPRx_L | xAMPRx_M | xAMPRx_S | xAMPRx_SS_16Kb |
> xAMPRx_V; \
>
> \
> if (type != __KM_CACHE)
> \
> - asm volatile("movgs %0,dampr"#ampr :: "r"(dampr) :
> "memory"); \
> + asm volatile("movgs %0,dampr"#ampr : : "r"(dampr) :
> "memory"); \
> else
> \
> asm volatile("movgs %0,iampr"#ampr"\n"
> \
> "movgs %0,dampr"#ampr"\n"
> \
> - :: "r"(dampr) : "memory"
> \
> + : : "r"(dampr) : "memory"
> \
> );
> \
>
> \
> asm("movsg damlr"#ampr",%0" : "=r"(damlr));
> \
>
> \
> /*printk("DAMR"#ampr": PRIM sl=%d L=%08lx P=%08lx\n", type, damlr,
> dampr);*/ \
> @@ -138,13 +138,13 @@
> }
> }
>
> #define __kunmap_atomic_primary(type, ampr) \
> do { \
> - asm volatile("movgs gr0,dampr"#ampr"\n" ::: "memory"); \
> + asm volatile("movgs gr0,dampr"#ampr"\n" : : : "memory");
> \
> if (type == __KM_CACHE) \
> - asm volatile("movgs gr0,iampr"#ampr"\n" ::: "memory"); \
> + asm volatile("movgs gr0,iampr"#ampr"\n" : : : "memory");
> \
> } while(0)
>
> #define __kunmap_atomic_secondary(slot, vaddr) \
> do { \
> asm volatile("tlbpr %0,gr0,#4,#1" : : "r"(vaddr) : "memory"); \
> diff -U 5 -r linux-2.6.24.7/include/asm-frv/module.h
> linux-2.6.24.7-patched/include/asm-frv/module.h
> --- linux-2.6.24.7/include/asm-frv/module.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-frv/module.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -9,13 +9,11 @@
> * 2 of the License, or (at your option) any later version.
> */
> #ifndef _ASM_MODULE_H
> #define _ASM_MODULE_H
>
> -struct mod_arch_specific
> -{
> -};
> +EMPTY_STRUCT_DECL(mod_arch_specific);
>
> #define Elf_Shdr Elf32_Shdr
> #define Elf_Sym Elf32_Sym
> #define Elf_Ehdr Elf32_Ehdr
>
> diff -U 5 -r linux-2.6.24.7/include/asm-frv/pgtable.h
> linux-2.6.24.7-patched/include/asm-frv/pgtable.h
> --- linux-2.6.24.7/include/asm-frv/pgtable.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-frv/pgtable.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -174,11 +174,11 @@
> * hook is made available.
> */
> #define set_pte(pteptr, pteval) \
> do { \
> *(pteptr) = (pteval); \
> - asm volatile("dcf %M0" :: "U"(*pteptr)); \
> + asm volatile("dcf %M0" : : "U"(*pteptr)); \
> } while(0)
> #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
>
> /*
> * pgd_offset() returns a (pgd_t *)
> @@ -208,11 +208,11 @@
> * but the define is needed for a generic inline function.)
> */
> #define set_pgd(pgdptr, pgdval) \
> do { \
> memcpy((pgdptr), &(pgdval), sizeof(pgd_t)); \
> - asm volatile("dcf %M0" :: "U"(*(pgdptr))); \
> + asm volatile("dcf %M0" : : "U"(*(pgdptr))); \
> } while(0)
>
> static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
> {
> return (pud_t *) pgd;
> @@ -389,25 +389,25 @@
> static inline pte_t pte_mkwrite(pte_t pte) { (pte).pte &= ~_PAGE_WP;
> return pte; }
>
> static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
> unsigned long addr, pte_t *ptep)
> {
> int i = test_and_clear_bit(_PAGE_BIT_ACCESSED, ptep);
> - asm volatile("dcf %M0" :: "U"(*ptep));
> + asm volatile("dcf %M0" : : "U"(*ptep));
> return i;
> }
>
> static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long
> addr, pte_t *ptep)
> {
> unsigned long x = xchg(&ptep->pte, 0);
> - asm volatile("dcf %M0" :: "U"(*ptep));
> + asm volatile("dcf %M0" : : "U"(*ptep));
> return __pte(x);
> }
>
> static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long
> addr, pte_t *ptep)
> {
> set_bit(_PAGE_BIT_WP, ptep);
> - asm volatile("dcf %M0" :: "U"(*ptep));
> + asm volatile("dcf %M0" : : "U"(*ptep));
> }
>
> /*
> * Macro to mark a page protection value as "uncacheable"
> */
> diff -U 5 -r linux-2.6.24.7/include/asm-frv/processor.h
> linux-2.6.24.7-patched/include/asm-frv/processor.h
> --- linux-2.6.24.7/include/asm-frv/processor.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-frv/processor.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -109,13 +109,13 @@
> /* Free all resources held by a thread. */
> static inline void release_thread(struct task_struct *dead_task)
> {
> }
>
> -extern asmlinkage int kernel_thread(int (*fn)(void *), void * arg,
> unsigned long flags);
> -extern asmlinkage void save_user_regs(struct user_context *target);
> -extern asmlinkage void *restore_user_regs(const struct user_context
> *target, ...);
> +asmlinkage int kernel_thread(int (*fn)(void *), void * arg, unsigned long
> flags);
> +asmlinkage void save_user_regs(struct user_context *target);
> +asmlinkage void *restore_user_regs(const struct user_context *target,
> ...);
>
> #define copy_segments(tsk, mm) do { } while (0)
> #define release_segments(mm) do { } while (0)
> #define forget_segments() do { } while (0)
>
> diff -U 5 -r linux-2.6.24.7/include/asm-frv/spr-regs.h
> linux-2.6.24.7-patched/include/asm-frv/spr-regs.h
> --- linux-2.6.24.7/include/asm-frv/spr-regs.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-frv/spr-regs.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -327,11 +327,11 @@
> asm volatile("movsg dampr"R",%0" : "=r"(_dampr)); \
> } while(0)
>
> #define restore_dampr(R, _dampr) \
> do { \
> - asm volatile("movgs %0,dampr"R :: "r"(_dampr)); \
> + asm volatile("movgs %0,dampr"R : : "r"(_dampr)); \
> } while(0)
>
> /*
> * AMCR - Address Mapping Control Register
> */
> diff -U 5 -r linux-2.6.24.7/include/asm-frv/system.h
> linux-2.6.24.7-patched/include/asm-frv/system.h
> --- linux-2.6.24.7/include/asm-frv/system.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-frv/system.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -20,11 +20,11 @@
> /*
> * switch_to(prev, next) should switch from task `prev' to `next'
> * `prev' will never be the same as `next'.
> * The `mb' is to tell GCC not to cache `current' across this call.
> */
> -extern asmlinkage
> +asmlinkage
> struct task_struct *__switch_to(struct thread_struct *prev_thread,
> struct thread_struct *next_thread,
> struct task_struct *prev);
>
> #define switch_to(prev, next, last) \
> @@ -172,11 +172,11 @@
> ((__get_PSR() & PSR_PIL) >= PSR_PIL_14)
>
> /*
> * Force strict CPU ordering.
> */
> -#define nop() asm volatile ("nop"::)
> +#define nop() asm volatile ("nop": :)
> #define mb() asm volatile ("membar" : : :"memory")
> #define rmb() asm volatile ("membar" : : :"memory")
> #define wmb() asm volatile ("membar" : : :"memory")
> #define set_mb(var, value) do { var = value; mb(); } while (0)
>
> diff -U 5 -r linux-2.6.24.7/include/asm-generic/bitops/hweight.h
> linux-2.6.24.7-patched/include/asm-generic/bitops/hweight.h
> --- linux-2.6.24.7/include/asm-generic/bitops/hweight.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-generic/bitops/hweight.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -1,11 +1,17 @@
> #ifndef _ASM_GENERIC_BITOPS_HWEIGHT_H_
> #define _ASM_GENERIC_BITOPS_HWEIGHT_H_
>
> #include <asm/types.h>
>
> +#if defined(__cplusplus)
> +extern "C" {
> +#endif
> extern unsigned int hweight32(unsigned int w);
> extern unsigned int hweight16(unsigned int w);
> extern unsigned int hweight8(unsigned int w);
> extern unsigned long hweight64(__u64 w);
> +#if defined(__cplusplus)
> +}
> +#endif
>
> #endif /* _ASM_GENERIC_BITOPS_HWEIGHT_H_ */
> diff -U 5 -r linux-2.6.24.7/include/asm-h8300/bitops.h
> linux-2.6.24.7-patched/include/asm-h8300/bitops.h
> --- linux-2.6.24.7/include/asm-h8300/bitops.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-h8300/bitops.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -37,11 +37,11 @@
> return result;
> }
>
> #define H8300_GEN_BITOP_CONST(OP,BIT) \
> case BIT: \
> - __asm__(OP " #" #BIT ",@%0"::"r"(b_addr):"memory"); \
> + __asm__(OP " #" #BIT ",@%0": :"r"(b_addr):"memory"); \
> break;
>
> #define H8300_GEN_BITOP(FNAME,OP) \
> static __inline__ void FNAME(int nr, volatile unsigned long* addr) \
> { \
> @@ -57,11 +57,11 @@
> H8300_GEN_BITOP_CONST(OP,5) \
> H8300_GEN_BITOP_CONST(OP,6) \
> H8300_GEN_BITOP_CONST(OP,7) \
> } \
> } else { \
> - __asm__(OP " %w0,@%1"::"r"(nr),"r"(b_addr):"memory"); \
> + __asm__(OP " %w0,@%1": :"r"(nr),"r"(b_addr):"memory"); \
> } \
> }
>
> /*
> * clear_bit() doesn't provide any barrier for the compiler.
> diff -U 5 -r linux-2.6.24.7/include/asm-h8300/module.h
> linux-2.6.24.7-patched/include/asm-h8300/module.h
> --- linux-2.6.24.7/include/asm-h8300/module.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-h8300/module.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -1,11 +1,11 @@
> #ifndef _ASM_H8300_MODULE_H
> #define _ASM_H8300_MODULE_H
> /*
> * This file contains the H8/300 architecture specific module code.
> */
> -struct mod_arch_specific { };
> +EMPTY_STRUCT_DECL(mod_arch_specific);
> #define Elf_Shdr Elf32_Shdr
> #define Elf_Sym Elf32_Sym
> #define Elf_Ehdr Elf32_Ehdr
>
> #define MODULE_SYMBOL_PREFIX "_"
> diff -U 5 -r linux-2.6.24.7/include/asm-h8300/system.h
> linux-2.6.24.7-patched/include/asm-h8300/system.h
> --- linux-2.6.24.7/include/asm-h8300/system.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-h8300/system.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -76,11 +76,11 @@
>
> /*
> * Force strict CPU ordering.
> * Not really required on H8...
> */
> -#define nop() asm volatile ("nop"::)
> +#define nop() asm volatile ("nop": :)
> #define mb() asm volatile ("" : : :"memory")
> #define rmb() asm volatile ("" : : :"memory")
> #define wmb() asm volatile ("" : : :"memory")
> #define set_mb(var, value) do { xchg(&var, value); } while (0)
>
> diff -U 5 -r linux-2.6.24.7/include/asm-ia64/gcc_intrin.h
> linux-2.6.24.7-patched/include/asm-ia64/gcc_intrin.h
> --- linux-2.6.24.7/include/asm-ia64/gcc_intrin.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-ia64/gcc_intrin.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -11,45 +11,45 @@
> /* define this macro to get some asm stmts included in 'c' files */
> #define ASM_SUPPORTED
>
> /* Optimization barrier */
> /* The "volatile" is due to gcc bugs */
> -#define ia64_barrier() asm volatile ("":::"memory")
> +#define ia64_barrier() asm volatile ("": : :"memory")
>
> -#define ia64_stop() asm volatile (";;"::)
> +#define ia64_stop() asm volatile (";;": :)
>
> -#define ia64_invala_gr(regnum) asm volatile ("invala.e r%0" ::
> "i"(regnum))
> +#define ia64_invala_gr(regnum) asm volatile ("invala.e r%0" : :
> "i"(regnum))
>
> -#define ia64_invala_fr(regnum) asm volatile ("invala.e f%0" ::
> "i"(regnum))
> +#define ia64_invala_fr(regnum) asm volatile ("invala.e f%0" : :
> "i"(regnum))
>
> extern void ia64_bad_param_for_setreg (void);
> extern void ia64_bad_param_for_getreg (void);
>
> register unsigned long ia64_r13 asm ("r13") __attribute_used__;
>
> #define ia64_setreg(regnum, val)
> \
> ({
> \
> switch (regnum) {
> \
> case _IA64_REG_PSR_L:
> \
> - asm volatile ("mov psr.l=%0" :: "r"(val) : "memory");
> \
> + asm volatile ("mov psr.l=%0" : : "r"(val) : "memory");
> \
> break;
> \
> case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC:
> \
> - asm volatile ("mov ar%0=%1" ::
> \
> + asm volatile ("mov ar%0=%1" : :
> \
> "i" (regnum - _IA64_REG_AR_KR0),
> \
> "r"(val): "memory");
> \
> break;
> \
> case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1:
> \
> - asm volatile ("mov cr%0=%1" ::
> \
> + asm volatile ("mov cr%0=%1" : :
> \
> "i" (regnum - _IA64_REG_CR_DCR),
> \
> "r"(val): "memory" );
> \
> break;
> \
> case _IA64_REG_SP:
> \
> - asm volatile ("mov r12=%0" ::
> \
> + asm volatile ("mov r12=%0" : :
> \
> "r"(val): "memory");
> \
> break;
> \
> case _IA64_REG_GP:
> \
> - asm volatile ("mov gp=%0" :: "r"(val) : "memory");
> \
> + asm volatile ("mov gp=%0" : : "r"(val) : "memory");
> \
> break;
> \
> default:
> \
> ia64_bad_param_for_setreg();
> \
> break;
> \
> }
> \
> @@ -94,11 +94,11 @@
>
> #define ia64_hint(mode) \
> ({ \
> switch (mode) { \
> case ia64_hint_pause: \
> - asm volatile ("hint @pause" ::: "memory"); \
> + asm volatile ("hint @pause" : : : "memory"); \
> break; \
> } \
> })
>
>
> @@ -197,35 +197,35 @@
> })
>
> #define ia64_stfs(x, regnum) \
> ({ \
> register double __f__ asm ("f"#regnum); \
> - asm volatile ("stfs [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
> + asm volatile ("stfs [%0]=%1" : : "r"(x), "f"(__f__) : "memory");
> \
> })
>
> #define ia64_stfd(x, regnum) \
> ({ \
> register double __f__ asm ("f"#regnum); \
> - asm volatile ("stfd [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
> + asm volatile ("stfd [%0]=%1" : : "r"(x), "f"(__f__) : "memory");
> \
> })
>
> #define ia64_stfe(x, regnum) \
> ({ \
> register double __f__ asm ("f"#regnum); \
> - asm volatile ("stfe [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
> + asm volatile ("stfe [%0]=%1" : : "r"(x), "f"(__f__) : "memory");
> \
> })
>
> #define ia64_stf8(x, regnum) \
> ({ \
> register double __f__ asm ("f"#regnum); \
> - asm volatile ("stf8 [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
> + asm volatile ("stf8 [%0]=%1" : : "r"(x), "f"(__f__) : "memory");
> \
> })
>
> #define ia64_stf_spill(x, regnum)
> \
> ({
> \
> register double __f__ asm ("f"#regnum);
> \
> - asm volatile ("stf.spill [%0]=%1" :: "r"(x), "f"(__f__) :
> "memory"); \
> + asm volatile ("stf.spill [%0]=%1" : : "r"(x), "f"(__f__) :
> "memory"); \
> })
>
> #define ia64_fetchadd4_acq(p, inc)
> \
> ({
> \
>
> \
> @@ -301,141 +301,141 @@
> })
>
> #define ia64_cmpxchg1_acq(ptr, new, old)
> \
> ({
> \
> __u64 ia64_intri_res;
> \
> - asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));
> \
> + asm volatile ("mov ar.ccv=%0;;" : : "rO"(old));
> \
> asm volatile ("cmpxchg1.acq %0=[%1],%2,ar.ccv":
> \
> "=r"(ia64_intri_res) : "r"(ptr), "r"(new) :
> "memory"); \
> ia64_intri_res;
> \
> })
>
> #define ia64_cmpxchg1_rel(ptr, new, old)
> \
> ({
> \
> __u64 ia64_intri_res;
> \
> - asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));
> \
> + asm volatile ("mov ar.ccv=%0;;" : : "rO"(old));
> \
> asm volatile ("cmpxchg1.rel %0=[%1],%2,ar.ccv":
> \
> "=r"(ia64_intri_res) : "r"(ptr), "r"(new) :
> "memory"); \
> ia64_intri_res;
> \
> })
>
> #define ia64_cmpxchg2_acq(ptr, new, old)
> \
> ({
> \
> __u64 ia64_intri_res;
> \
> - asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));
> \
> + asm volatile ("mov ar.ccv=%0;;" : : "rO"(old));
> \
> asm volatile ("cmpxchg2.acq %0=[%1],%2,ar.ccv":
> \
> "=r"(ia64_intri_res) : "r"(ptr), "r"(new) :
> "memory"); \
> ia64_intri_res;
> \
> })
>
> #define ia64_cmpxchg2_rel(ptr, new, old)
> \
> ({
> \
> __u64 ia64_intri_res;
> \
> - asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));
> \
> + asm volatile ("mov ar.ccv=%0;;" : : "rO"(old));
> \
>
> \
> asm volatile ("cmpxchg2.rel %0=[%1],%2,ar.ccv":
> \
> "=r"(ia64_intri_res) : "r"(ptr), "r"(new) :
> "memory"); \
> ia64_intri_res;
> \
> })
>
> #define ia64_cmpxchg4_acq(ptr, new, old)
> \
> ({
> \
> __u64 ia64_intri_res;
> \
> - asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));
> \
> + asm volatile ("mov ar.ccv=%0;;" : : "rO"(old));
> \
> asm volatile ("cmpxchg4.acq %0=[%1],%2,ar.ccv":
> \
> "=r"(ia64_intri_res) : "r"(ptr), "r"(new) :
> "memory"); \
> ia64_intri_res;
> \
> })
>
> #define ia64_cmpxchg4_rel(ptr, new, old)
> \
> ({
> \
> __u64 ia64_intri_res;
> \
> - asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));
> \
> + asm volatile ("mov ar.ccv=%0;;" : : "rO"(old));
> \
> asm volatile ("cmpxchg4.rel %0=[%1],%2,ar.ccv":
> \
> "=r"(ia64_intri_res) : "r"(ptr), "r"(new) :
> "memory"); \
> ia64_intri_res;
> \
> })
>
> #define ia64_cmpxchg8_acq(ptr, new, old)
> \
> ({
> \
> __u64 ia64_intri_res;
> \
> - asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));
> \
> + asm volatile ("mov ar.ccv=%0;;" : : "rO"(old));
> \
> asm volatile ("cmpxchg8.acq %0=[%1],%2,ar.ccv":
> \
> "=r"(ia64_intri_res) : "r"(ptr), "r"(new) :
> "memory"); \
> ia64_intri_res;
> \
> })
>
> #define ia64_cmpxchg8_rel(ptr, new, old)
> \
> ({
> \
> __u64 ia64_intri_res;
> \
> - asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));
> \
> + asm volatile ("mov ar.ccv=%0;;" : : "rO"(old));
> \
>
> \
> asm volatile ("cmpxchg8.rel %0=[%1],%2,ar.ccv":
> \
> "=r"(ia64_intri_res) : "r"(ptr), "r"(new) :
> "memory"); \
> ia64_intri_res;
> \
> })
>
> -#define ia64_mf() asm volatile ("mf" ::: "memory")
> -#define ia64_mfa() asm volatile ("mf.a" ::: "memory")
> +#define ia64_mf() asm volatile ("mf" : : : "memory")
> +#define ia64_mfa() asm volatile ("mf.a" : : : "memory")
>
> -#define ia64_invala() asm volatile ("invala" ::: "memory")
> +#define ia64_invala() asm volatile ("invala" : : : "memory")
>
> #define ia64_thash(addr)
> \
> ({
> \
> __u64 ia64_intri_res;
> \
> asm volatile ("thash %0=%1" : "=r"(ia64_intri_res) : "r" (addr));
> \
> ia64_intri_res;
> \
> })
>
> -#define ia64_srlz_i() asm volatile (";; srlz.i ;;" ::: "memory")
> -#define ia64_srlz_d() asm volatile (";; srlz.d" ::: "memory");
> +#define ia64_srlz_i() asm volatile (";; srlz.i ;;" : : : "memory")
> +#define ia64_srlz_d() asm volatile (";; srlz.d" : : : "memory");
>
> #ifdef HAVE_SERIALIZE_DIRECTIVE
> # define ia64_dv_serialize_data() asm volatile
> (".serialize.data");
> # define ia64_dv_serialize_instruction() asm volatile
> (".serialize.instruction");
> #else
> # define ia64_dv_serialize_data()
> # define ia64_dv_serialize_instruction()
> #endif
>
> -#define ia64_nop(x) asm volatile ("nop %0"::"i"(x));
> +#define ia64_nop(x) asm volatile ("nop %0": :"i"(x));
>
> -#define ia64_itci(addr) asm volatile ("itc.i %0;;" :: "r"(addr) :
> "memory")
> +#define ia64_itci(addr) asm volatile ("itc.i %0;;" : : "r"(addr) :
> "memory")
>
> -#define ia64_itcd(addr) asm volatile ("itc.d %0;;" :: "r"(addr) :
> "memory")
> +#define ia64_itcd(addr) asm volatile ("itc.d %0;;" : : "r"(addr) :
> "memory")
>
>
> #define ia64_itri(trnum, addr) asm volatile ("itr.i itr[%0]=%1"
> \
> - :: "r"(trnum), "r"(addr) :
> "memory")
> + : : "r"(trnum), "r"(addr) :
> "memory")
>
> #define ia64_itrd(trnum, addr) asm volatile ("itr.d dtr[%0]=%1"
> \
> - :: "r"(trnum), "r"(addr) :
> "memory")
> + : : "r"(trnum), "r"(addr) :
> "memory")
>
> #define ia64_tpa(addr)
> \
> ({
> \
> __u64 ia64_pa;
> \
> asm volatile ("tpa %0 = %1" : "=r"(ia64_pa) : "r"(addr) : "memory");
> \
> ia64_pa;
> \
> })
>
> #define __ia64_set_dbr(index, val)
> \
> - asm volatile ("mov dbr[%0]=%1" :: "r"(index), "r"(val) : "memory")
> + asm volatile ("mov dbr[%0]=%1" : : "r"(index), "r"(val) : "memory")
>
> #define ia64_set_ibr(index, val)
> \
> - asm volatile ("mov ibr[%0]=%1" :: "r"(index), "r"(val) : "memory")
> + asm volatile ("mov ibr[%0]=%1" : : "r"(index), "r"(val) : "memory")
>
> #define ia64_set_pkr(index, val)
> \
> - asm volatile ("mov pkr[%0]=%1" :: "r"(index), "r"(val) : "memory")
> + asm volatile ("mov pkr[%0]=%1" : : "r"(index), "r"(val) : "memory")
>
> #define ia64_set_pmc(index, val)
> \
> - asm volatile ("mov pmc[%0]=%1" :: "r"(index), "r"(val) : "memory")
> + asm volatile ("mov pmc[%0]=%1" : : "r"(index), "r"(val) : "memory")
>
> #define ia64_set_pmd(index, val)
> \
> - asm volatile ("mov pmd[%0]=%1" :: "r"(index), "r"(val) : "memory")
> + asm volatile ("mov pmd[%0]=%1" : : "r"(index), "r"(val) : "memory")
>
> #define ia64_set_rr(index, val)
> \
> - asm volatile ("mov rr[%0]=%1" :: "r"(index), "r"(val) : "memory");
> + asm volatile ("mov rr[%0]=%1" : : "r"(index), "r"(val) : "memory");
>
> #define ia64_get_cpuid(index)
> \
> ({
> \
> __u64 ia64_intri_res;
> \
> asm volatile ("mov %0=cpuid[%r1]" : "=r"(ia64_intri_res) :
> "rO"(index)); \
> @@ -483,39 +483,39 @@
> __u64 ia64_intri_res;
> \
> asm volatile ("mov %0=rr[%1]" : "=r"(ia64_intri_res) : "r" (index));
> \
> ia64_intri_res;
> \
> })
>
> -#define ia64_fc(addr) asm volatile ("fc %0" :: "r"(addr) : "memory")
> +#define ia64_fc(addr) asm volatile ("fc %0" : : "r"(addr) : "memory")
>
>
> -#define ia64_sync_i() asm volatile (";; sync.i" ::: "memory")
> +#define ia64_sync_i() asm volatile (";; sync.i" : : : "memory")
>
> -#define ia64_ssm(mask) asm volatile ("ssm %0":: "i"((mask)) : "memory")
> -#define ia64_rsm(mask) asm volatile ("rsm %0":: "i"((mask)) : "memory")
> -#define ia64_sum(mask) asm volatile ("sum %0":: "i"((mask)) : "memory")
> -#define ia64_rum(mask) asm volatile ("rum %0":: "i"((mask)) : "memory")
> +#define ia64_ssm(mask) asm volatile ("ssm %0": : "i"((mask)) : "memory")
> +#define ia64_rsm(mask) asm volatile ("rsm %0": : "i"((mask)) : "memory")
> +#define ia64_sum(mask) asm volatile ("sum %0": : "i"((mask)) : "memory")
> +#define ia64_rum(mask) asm volatile ("rum %0": : "i"((mask)) : "memory")
>
> -#define ia64_ptce(addr) asm volatile ("ptc.e %0" :: "r"(addr))
> +#define ia64_ptce(addr) asm volatile ("ptc.e %0" : : "r"(addr))
>
> #define ia64_ptcga(addr, size)
> \
> do {
> \
> - asm volatile ("ptc.ga %0,%1" :: "r"(addr), "r"(size) : "memory");
> \
> + asm volatile ("ptc.ga %0,%1" : : "r"(addr), "r"(size) : "memory");
> \
> ia64_dv_serialize_data();
> \
> } while (0)
>
> #define ia64_ptcl(addr, size)
> \
> do {
> \
> - asm volatile ("ptc.l %0,%1" :: "r"(addr), "r"(size) : "memory");
> \
> + asm volatile ("ptc.l %0,%1" : : "r"(addr), "r"(size) : "memory");
> \
> ia64_dv_serialize_data();
> \
> } while (0)
>
> #define ia64_ptri(addr, size) \
> - asm volatile ("ptr.i %0,%1" :: "r"(addr), "r"(size) : "memory")
> + asm volatile ("ptr.i %0,%1" : : "r"(addr), "r"(size) : "memory")
>
> #define ia64_ptrd(addr, size) \
> - asm volatile ("ptr.d %0,%1" :: "r"(addr), "r"(size) : "memory")
> + asm volatile ("ptr.d %0,%1" : : "r"(addr), "r"(size) : "memory")
>
> /* Values for lfhint in ia64_lfetch and ia64_lfetch_fault */
>
> #define ia64_lfhint_none 0
> #define ia64_lfhint_nt1 1
> @@ -542,20 +542,20 @@
>
> #define ia64_lfetch_excl(lfhint, y) \
> ({ \
> switch (lfhint) { \
> case ia64_lfhint_none: \
> - asm volatile ("lfetch.excl [%0]" :: "r"(y)); \
> + asm volatile ("lfetch.excl [%0]" : : "r"(y)); \
> break; \
> case ia64_lfhint_nt1: \
> - asm volatile ("lfetch.excl.nt1 [%0]" :: "r"(y)); \
> + asm volatile ("lfetch.excl.nt1 [%0]" : : "r"(y)); \
> break; \
> case ia64_lfhint_nt2: \
> - asm volatile ("lfetch.excl.nt2 [%0]" :: "r"(y)); \
> + asm volatile ("lfetch.excl.nt2 [%0]" : : "r"(y)); \
> break; \
> case ia64_lfhint_nta: \
> - asm volatile ("lfetch.excl.nta [%0]" :: "r"(y)); \
> + asm volatile ("lfetch.excl.nta [%0]" : : "r"(y)); \
> break; \
> } \
> })
>
> #define ia64_lfetch_fault(lfhint, y) \
> @@ -578,29 +578,29 @@
>
> #define ia64_lfetch_fault_excl(lfhint, y) \
> ({ \
> switch (lfhint) { \
> case ia64_lfhint_none: \
> - asm volatile ("lfetch.fault.excl [%0]" :: "r"(y)); \
> + asm volatile ("lfetch.fault.excl [%0]" : : "r"(y)); \
> break; \
> case ia64_lfhint_nt1: \
> - asm volatile ("lfetch.fault.excl.nt1 [%0]" :: "r"(y)); \
> + asm volatile ("lfetch.fault.excl.nt1 [%0]" : : "r"(y));
> \
> break; \
> case ia64_lfhint_nt2: \
> - asm volatile ("lfetch.fault.excl.nt2 [%0]" :: "r"(y)); \
> + asm volatile ("lfetch.fault.excl.nt2 [%0]" : : "r"(y));
> \
> break; \
> case ia64_lfhint_nta: \
> - asm volatile ("lfetch.fault.excl.nta [%0]" :: "r"(y)); \
> + asm volatile ("lfetch.fault.excl.nta [%0]" : : "r"(y));
> \
> break; \
> } \
> })
>
> #define ia64_intrin_local_irq_restore(x) \
> do { \
> asm volatile (";; cmp.ne p6,p7=%0,r0;;" \
> "(p6) ssm psr.i;" \
> "(p7) rsm psr.i;;" \
> "(p6) srlz.d" \
> - :: "r"((x)) : "p6", "p7", "memory"); \
> + : : "r"((x)) : "p6", "p7", "memory"); \
> } while (0)
>
> #endif /* _ASM_IA64_GCC_INTRIN_H */
> diff -U 5 -r linux-2.6.24.7/include/asm-ia64/spinlock.h
> linux-2.6.24.7-patched/include/asm-ia64/spinlock.h
> --- linux-2.6.24.7/include/asm-ia64/spinlock.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-ia64/spinlock.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -89,11 +89,11 @@
> #define __raw_spin_lock(lock) __raw_spin_lock_flags(lock, 0)
>
> /* Unlock by doing an ordered store and releasing the cacheline with nta
> */
> static inline void __raw_spin_unlock(raw_spinlock_t *x) {
> barrier();
> - asm volatile ("st4.rel.nta [%0] = r0\n\t" :: "r"(x));
> + asm volatile ("st4.rel.nta [%0] = r0\n\t" : : "r"(x));
> }
>
> #else /* !ASM_SUPPORTED */
> #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
> # define __raw_spin_lock(x)
> \
> @@ -148,11 +148,11 @@
> "cmp4.eq p0,p7 = r0,r2\n"
> \
> "(p7) br.cond.spnt.few 1b \n"
> \
> "cmpxchg4.acq r2 = [%0], r29, ar.ccv;;\n"
> \
> "cmp4.eq p0,p7 = r0, r2\n"
> \
> "(p7) br.cond.spnt.few 1b;;\n"
> \
> - :: "r"(rw) : "ar.ccv", "p7", "r2", "r29", "memory");
> \
> + : : "r"(rw) : "ar.ccv", "p7", "r2", "r29", "memory");
> \
> } while(0)
>
> #define __raw_write_trylock(rw)
> \
> ({
> \
> register long result;
> \
> @@ -167,11 +167,11 @@
>
> static inline void __raw_write_unlock(raw_rwlock_t *x)
> {
> u8 *y = (u8 *)x;
> barrier();
> - asm volatile ("st1.rel.nta [%0] = r0\n\t" :: "r"(y+3) : "memory" );
> + asm volatile ("st1.rel.nta [%0] = r0\n\t" : : "r"(y+3) : "memory"
> );
> }
>
> #else /* !ASM_SUPPORTED */
>
> #define __raw_write_lock(l)
> \
> diff -U 5 -r linux-2.6.24.7/include/asm-m32r/module.h
> linux-2.6.24.7-patched/include/asm-m32r/module.h
> --- linux-2.6.24.7/include/asm-m32r/module.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-m32r/module.h 2008-11-19
> 16:47:19.000000000 -0600
> @@ -1,9 +1,9 @@
> #ifndef _ASM_M32R_MODULE_H
> #define _ASM_M32R_MODULE_H
>
> -struct mod_arch_specific { };
> +EMPTY_STRUCT_DECL(mod_arch_specific);
>
> #define Elf_Shdr Elf32_Shdr
> #define Elf_Sym Elf32_Sym
> #define Elf_Ehdr Elf32_Ehdr
>
> diff -U 5 -r linux-2.6.24.7/include/asm-m68k/system.h
> linux-2.6.24.7-patched/include/asm-m68k/system.h
> --- linux-2.6.24.7/include/asm-m68k/system.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-m68k/system.h 2008-11-19
> 16:47:20.000000000 -0600
> @@ -161,27 +161,27 @@
> */
> #ifdef CONFIG_RMW_INSNS
> #define __HAVE_ARCH_CMPXCHG 1
>
> static inline unsigned long __cmpxchg(volatile void *p, unsigned long old,
> - unsigned long new, int size)
> + unsigned long n, int size)
> {
> switch (size) {
> case 1:
> __asm__ __volatile__ ("casb %0,%2,%1"
> : "=d" (old), "=m" (*(char *)p)
> - : "d" (new), "0" (old), "m" (*(char
> *)p));
> + : "d" (n), "0" (old), "m" (*(char
> *)p));
> break;
> case 2:
> __asm__ __volatile__ ("casw %0,%2,%1"
> : "=d" (old), "=m" (*(short *)p)
> - : "d" (new), "0" (old), "m" (*(short
> *)p));
> + : "d" (n), "0" (old), "m" (*(short
> *)p));
> break;
> case 4:
> __asm__ __volatile__ ("casl %0,%2,%1"
> : "=d" (old), "=m" (*(int *)p)
> - : "d" (new), "0" (old), "m" (*(int
> *)p));
> + : "d" (n), "0" (old), "m" (*(int
> *)p));
> break;
> }
> return old;
> }
>
> diff -U 5 -r linux-2.6.24.7/include/asm-m68knommu/mcfwdebug.h
> linux-2.6.24.7-patched/include/asm-m68knommu/mcfwdebug.h
> --- linux-2.6.24.7/include/asm-m68knommu/mcfwdebug.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-m68knommu/mcfwdebug.h 2008-11-19
> 16:47:20.000000000 -0600
> @@ -106,13 +106,13 @@
> #if 0
> // This strain is for gas which doesn't have the wdebug instructions
> defined
> asm( "move.l %0, %%a0\n\t"
> ".word 0xfbd0\n\t"
> ".word 0x0003\n\t"
> - :: "g" (dbg) : "a0");
> + : : "g" (dbg) : "a0");
> #else
> // And this is for when it does
> - asm( "wdebug (%0)" :: "a" (dbg));
> + asm( "wdebug (%0)" : : "a" (dbg));
> #endif
> }
>
> #endif
> diff -U 5 -r linux-2.6.24.7/include/asm-m68knommu/system.h
> linux-2.6.24.7-patched/include/asm-m68knommu/system.h
> --- linux-2.6.24.7/include/asm-m68knommu/system.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-m68knommu/system.h 2008-11-19
> 16:47:20.000000000 -0600
> @@ -98,11 +98,11 @@
>
> /*
> * Force strict CPU ordering.
> * Not really required on m68k...
> */
> -#define nop() asm volatile ("nop"::)
> +#define nop() asm volatile ("nop": :)
> #define mb() asm volatile ("" : : :"memory")
> #define rmb() asm volatile ("" : : :"memory")
> #define wmb() asm volatile ("" : : :"memory")
> #define set_mb(var, value) do { xchg(&var, value); } while (0)
>
> @@ -192,18 +192,18 @@
> * indicated by comparing RETURN with OLD.
> */
> #define __HAVE_ARCH_CMPXCHG 1
>
> static __inline__ unsigned long
> -cmpxchg(volatile int *p, int old, int new)
> +cmpxchg(volatile int *p, int old, int n)
> {
> unsigned long flags;
> int prev;
>
> local_irq_save(flags);
> if ((prev = *p) == old)
> - *p = new;
> + *p = n;
> local_irq_restore(flags);
> return(prev);
> }
>
>
> diff -U 5 -r linux-2.6.24.7/include/asm-mips/edac.h
> linux-2.6.24.7-patched/include/asm-mips/edac.h
> --- linux-2.6.24.7/include/asm-mips/edac.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-mips/edac.h 2008-11-19
> 16:47:20.000000000 -0600
> @@ -12,11 +12,11 @@
> for (i = 0; i < size / sizeof(unsigned long); i++) {
> /*
> * Very carefully read and write to memory atomically
> * so we are interrupt, DMA and SMP safe.
> *
> - * Intel: asm("lock; addl $0, %0"::"m"(*virt_addr));
> + * Intel: asm("lock; addl $0, %0": :"m"(*virt_addr));
> */
>
> __asm__ __volatile__ (
> " .set mips2 \n"
> "1: ll %0, %1 # atomic_scrub \n"
> diff -U 5 -r linux-2.6.24.7/include/asm-mips/fpu.h
> linux-2.6.24.7-patched/include/asm-mips/fpu.h
> --- linux-2.6.24.7/include/asm-mips/fpu.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-mips/fpu.h 2008-11-19
> 16:47:20.000000000 -0600
> @@ -26,15 +26,15 @@
> #endif
>
> struct sigcontext;
> struct sigcontext32;
>
> -extern asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
> -extern asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
> +asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
> +asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
>
> -extern asmlinkage int (*save_fp_context32)(struct sigcontext32 __user
> *sc);
> -extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user
> *sc);
> +asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
> +asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
>
> extern void fpu_emulator_init_fpu(void);
> extern void _init_fpu(void);
> extern void _save_fp(struct task_struct *);
> extern void _restore_fp(struct task_struct *);
> diff -U 5 -r linux-2.6.24.7/include/asm-mips/io.h
> linux-2.6.24.7-patched/include/asm-mips/io.h
> --- linux-2.6.24.7/include/asm-mips/io.h 2008-05-06
> 18:22:34.000000000 -0500
> +++ linux-2.6.24.7-patched/include/asm-mips/io.h 2008-11-19
> 16:47:20.000000000 -0600
> @@ -453,22 +453,22 @@
> #define __BUILD_MEMORY_STRING(bwlq, type) \
> \
> static inline void writes##bwlq(volatile void __iomem *mem, \
> const void *addr, unsigned int count) \
> { \
> - const volatile type *__addr = addr; \
> + const volatile type *__addr = (const type *) addr; \
> \
> while (count--) { \
> __mem_write##bwlq(*__addr, mem); \
> __addr++; \
> } \
> } \
> \
> static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
> unsigned int count) \
> { \
> - volatile type *__addr = addr; \
> + volatile type *__addr = (const type *) addr; \
> \
> while (count--) { \
> *__addr = __mem_read##bwlq(mem); \
> __addr++; \
> } \
> @@ -477,22 +477,22 @@
> #define __BUILD_IOPORT_STRING(bwlq, type) \
> \
> static inline void outs##bwlq(unsigned long port, const void *addr, \
> unsigned int count) \
> { \
> - const volatile type *__addr = addr; \
> + const volatile type *__addr = (const type *) addr; \
> \
> while (count--) { \
> __mem_out##bwlq(*__addr, port); \
> __addr++; \
> } \
> } \
> \
> static inline void ins##bwlq(unsigned long port, void *addr, \
> unsigned int count) \
> { \
> - volatile type *__addr = addr; \
> + volatile type *__addr = (const type *) addr; \
> \
> while (count--) { \
> *__addr = __mem_in##bwlq(port); \
> __addr++; \
> } \
> @@ -510,11 +510,11 @@
> BUILDSTRING(q, u64)
> #endif
>
>
> /* Depends on MIPS II instruction set */
> -#define mmiowb(
> Index: target/linux/ixp4xx/Makefile
> ===================================================================
> --- target/linux/ixp4xx/Makefile (revision 11777)
> +++ target/linux/ixp4xx/Makefile (working copy)
> @@ -12,7 +12,7 @@
> FEATURES:=squashfs
> SUBTARGETS=generic harddisk
>
> -LINUX_VERSION:=2.6.26-rc9
> +LINUX_VERSION:=2.6.24.7
>
> include $(INCLUDE_DIR)/target.mk
>
>
> _______________________________________________
> click mailing list
> click at amsterdam.lcs.mit.edu
> https://amsterdam.lcs.mit.edu/mailman/listinfo/click
>
>
--
Yongheng Qi
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