Entering and leaving the kernel
Required reading: Chapter 9, 10, 11, and 12 (until sys1.c)
- Big picture: kernel is trusted-third party. Only kernel can
execute priviledge instructions (e.g., on PDP-11 loading segmentation
registers). The processor enforces this protection through the
user/kernel mode bit. (Where are those in the PDP-11? ans: bits 12-15
in PSW). If a user application needs a priviledged service, it must
ask the kernel to perform it on its behalf. How can a user program
change to the kernel address space? How can the kernel transfer to a
user address space? These questions are the topic of today's lecture.
- There are three events at which the processor should switch to the
kernel address space: (1) supervisor call (called a trap instruction
on the PDP-11); (2) an interrupt; and (3) an illegal instruction. (1)
corresponds to the case that user program wants to ask explicitly for
a kernel service (e.g., switching address spaces). (2) corresponds to
the case when a device asks for attention; since devices are shared,
we don't want an arbitrary user program to process the interrupt, so
the processor should switch control to the kernel. (3) corresponds to
the case that the user program got itself in a bad state; by
transfering control to the kernel, the kernel can clean up the user
- Although these three events are different, they all invoke the
same mechanism to transfer control to the kernel. This mechanism
consists of three steps: (a) change the processor to kernel mode; (b)
save and reload the MMU to switch to the kernel address space; and (c)
save the program counter and reload it with the kernel entry point.
The exact implementation of this mechanism differs from processor to
processor, but it is essential that the 3 steps together are atomic.
If not, a user program may run with the kernel mode bit, and thus
break the protection.
- Example: the PDP-11 implementation of this mechanism has 3 steps:
(1) save PSW and PC in internal registers; (2) PC and PSW are reloaded
from the vector location for the event that causes the switch; and (3)
push the internal registers (the saved PSW and PC) on to the new
active stack. Step 2 may switch the processor into kernel mode
depending on the bits set in loaded PSW (corresponding to step a) .
Step 2 loads the kernel entry point (corresponding to step c). Step 1
and 3 correspond to the saving part of step c. Note that step b is
implicit on the PDP-11, because in kernel mode the processor has its
own segment address registers and sp, thus the processor doesn't have
to save and reload the MMU explicitly. (On Wednesday we will see how
the x86 implements user to kernel switching.)
- Conceptually, returning from the kernel to a user address space
also has the same 3 steps as before: (a) change mode from kernel to
user; (b) reload MMU state; and (c) load PC that was saved on
entering. On the PDP-11, these 3 steps are performed by a single
instruction, rtt, which reloads the PSW and PC from the current
active stack. By reloading the PSW, the processor may switch to user
mode and switch to using user segment registers.
- Interrupts are a hardware implementation of sequence coordination.
Conceptually, an interrupt is the hardware equivalent of wakeup. If
the processor doesn't support interrupts, the processor has to
periodically check on the devices (which is called polling).
The problem with polling is how often should the processor poll; if
the processor polls to fast, then it wastes resources; if the
processor polls to slow, it may take a long time for a device receives
attention. Interrups avoid these problems.
Conceptually interrupts are implemented by adding a wire between
device and processor; when the device raises the signal on the wire,
it sets the "interrupted" gate on the processor. The processor checks
the gate between each instruction, and if the gate is set, it invokes
the kernel-entering mechanism described above. (The actual
implementation is more complicated: to support critical sections, the
processor can disable interrupts temporarily. Furthermore, the
processor might have multiple interrups levels, as the PDP-11 does.)
V6 code examples