Address spaces

Required reading: Chapter 2 and 6 of Lions's commentary

Overview

• Draw picture with multiple applications, kernel (another app), and hardware. OS provides a virtual computer to each application. The virtual computer's interface is the processor's instruction set and the system call interface.
• Goal: fault isolation between applications in picture
  • stores shouldn't be able to overwrite other apps's data
  • jmp shouldn't be able to enter another application
  • one application cannot hog the processor
• Method: give each applications its own virtual processor using threads (L6) and address spaces. Address spaces provide each application with the ideas that it has a complete memory for itself. all the addresses it issues are its addresses (e.g., each application has an address 0).
• Why does this work? load/stores/jmps cannot touch/enter another application's data/text
• How do you give each application its own address space?
  • Insert a memory management unit (MMU) between processor and memory
  • MMU translates virtual address to physical addresses using a translation table
  • Implementation approaches for translation table:
    1. for each virtual address store physical address (costly)
    2. translate a set of contiguous virtual addresses at a time using segments (segment #, base address, length)
       PDP-11 example: page address register (PAR) and page descriptor register (PDR). Note that physical addresses (18 bits) are bigger than virtual addresses (16 bits)
    3. translate a fixed-size set of address (page) at a time using a page map (page # -> block #) (draw hardware page table picture). Datastructures for page map: array, n-level tree, superpages, etc.
    
    Some processor have both 2+3: x86!
• What if two applications want to share real memory? Map the physical address twice, once in each address space
• How do you give an application access to a memory-mapped-IO device? Map the physical address for the device into the applications address space
• How to manage address spaces? That is, switching, creating, deleting, growing, mapping devices in, etc. Reuse the address ideas: have one address space that includes all others. This special address spaces can manage all address spaces then. This special address space is called the kernel address space. How to protect the kernel?
  • If kernel is unprotected, every application can access kernel page map, and thus all others.
  • Extend processor with mode bit (user, kernel) in kernel mode, application change change mode bit to user in user mode, applications are prohibited to change mode bit and to change address spaces in kernel mode, processor always runs in kernel address space
  • If user application wants to change address spaces, it has to ask the kernel. Next lecture we will see how.
    PDP-11 stores kernel/user mode in processor status word (PSW), PS in v6 code. PDP-11/40 two set of 8 segmentation registers, one for user mode, one for kernel mode. (On 11/40: also two copies of sp register.)
• How do you get off the ground?
  • when computer starts, MMU is disabled.
  • computer starts in kernel mode, with no translation (i.e., virtual address 0 is physical address 0, and so on)
  • kernel program sets up MMU to translate kernel address to physical address. often kernel virtual address translates to physical adress 0.
  • enable MMU
    Lab 1 and the Lions's chapters for today explores this topic in detail.

  Case study (Lions's book)

  • You will need to read most of the source code multiple times. Your goal is to explain every line to yourself without using the commentary. Read it one or multiple times with Lion's commentary until you reach the goal
  • PDP-11 assembly (8 general register, pc (r7), sp (r6), environment (r5)) r0, r1 used for results
  • JSR rn, label:
    1. push rn
    2. rn = pc
    3. pc = dest
  • We covered the lines 612 through 632, setting up part of the kernel virtual address space. These lines are explained by Lions in Chapter 6, but the accompanying picture may be helpful, since it depicts the end result.